参数资料
型号: AD7366BRUZ-5-RL7
厂商: Analog Devices Inc
文件页数: 2/28页
文件大小: 0K
描述: IC ADC 12BIT DUAL BIPO 24-TSSOP
设计资源: Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
标准包装: 1,000
系列: iCMOS®
位数: 12
采样率(每秒): 500k
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 2
功率耗散(最大): 88.8mW
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
输入数目和类型: 4 个单端,单极;4 个单端,双极
配用: EVAL-AD7366CBZ-ND - BOARD EVALUATION FOR AD7366
AD7366-5/AD7367-5
Rev. A | Page 10 of 28
Pin No.
Mnemonic
Description
18
REFSEL
Internal/External Reference Selection, Logic Input. If this pin is tied to logic high, the on-chip 2.5 V reference is
used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to
decoupling capacitors. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7366-5/
AD7367-5 through the DCAPA and/or DCAPB pins.
19
CS
Chip Select, Active Low Logic Input. This input frames the serial data transfer. When CS is logic low, the output bus
is enabled, and the conversion result is output on DOUTA and DOUTB.
20
SCLK
Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7366-5/AD7367-5.
21
CNVST
Conversion Start, Logic Input. This pin is edge triggered. On the falling edge of this input, the track/hold goes into
hold mode and the conversion is initiated. If CNVST is low at the end of a conversion, the part goes into power-
down mode. In this case, the rising edge of CNVST instructs the part to power up again.
22
BUSY
Busy Output. BUSY transitions high when a conversion starts and remains high until the conversion completes.
24
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7366-5/AD7367-5. The DGND
pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
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