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参数资料
| 型号： | AD7376AN100 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字电位计 |
| 英文描述： | +-15 V Operation Digital Potentiometer |
| 中文描述： | 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDIP14 |
| 封装： | PLASTIC, DIP-14 |
| 文件页数： | 2/12页 |
| 文件大小： | 335K |
| 代理商： | AD7376AN100 |
–2–
REV. 0
AD7376–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(V
DD
/V
SS
=
6
15 V
6
10% or
6
5 V
6
10%, V
A
= +V
DD
, V
B
= V
SS
/0 V, –40
8
C < T
A
< +85
8
C
unless otherwse noted.)
Parameter
Symbol
Conditions
Min
T yp
1
Max
Units
DC CHARACT ERIST ICS RHEOST AT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
Resistor Nonlinearity
2
Nominal Resistor T olerance
Resistance T emperature Coefficient
Wiper Resistance
Wiper Resistance
R-DNL
R-INL
R
R
AB
/
T
R
W
R
W
R
WB
, V
A
= NC
R
WB
, V
A
= NC
T
A
= +25
°
C
V
AB
= V
DD
, Wiper = No Connect
I
W
=
±
15 V/R
NOMINAL
I
W
=
±
5 V/R
NOMINAL
–1
–1
–30
±
0.25
±
0.5
+1
+1
30
LSB
LSB
%
ppm/
°
C
–300
120
200
200
DC CHARACT ERIST ICS POT ENT IOMET ER DIVIDER MODE (Specifications Apply to All VRs)
Resolution
N
Integral Nonlinearity
3
INL
Differential Nonlinearity
3
DNL
Voltage Divider T emperature Coefficient
V
W
/
T
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
7
–1
–1
Bits
LSB
LSB
ppm/
°
C
LSB
LSB
±
0.5
±
0.1
5
–0.5
+0.5
+1
+1
Code = 40
H
Code = 7F
H
Code = 00
H
–2
0
+0
+1
RESIST OR T ERMINALS
Voltage Range
4
Capacitance
5
A, B
Capacitance
5
W
Shutdown Supply Current
6
Shutdown Wiper Resistance
Common-Mode Leakage
V
A, B, W
C
A, B
C
W
I
A_SD
R
W_SD
I
CM
V
SS
V
DD
V
pF
pF
μ
A
nA
f = 1 MHz, Measured to GND, Code = 40
H
f = 1 MHz, Measured to GND, Code = 40
H
V
A
= V
DD
, V
B
= 0 V, SHDN = 0
V
A
= V
DD
, V
B
= 0 V, SHDN = 0, V
DD
= +15 V
V
A
= V
B
= V
W
45
60
0.01
170
1
1
400
DIGIT AL INPUT S AND OUT PUT S
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
7
Input Current
Input Capacitance
5
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
= +5 V or +15 V
V
DD
= +5 V or +15 V
R
L
= 2.2 k
to +5 V
I
OL
= 1.6 mA, V
LOGIC
= +5 V, V
DD
= +15 V
V
IN
= 0 V or +15 V
2.4
V
V
V
V
μ
A
pF
0.8
4.9
0.4
±
1
5
POWER SUPPLIES
Power Supply Range
Power Supply Range
Supply Current
Supply Current
Supply Current
Power Dissipation
8
Power Supply Sensitivity
V
DD
/V
SS
V
DD
I
DD
I
DD
I
SS
P
DISS
PSS
PSS
Dual Supply Range
Single Supply Range, V
SS
= 0
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +15 V
V
IH
= +5 V or V
IL
= 0 V, V
SS
= –5 V or –15 V
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +15 V, V
SS
= –15 V
V
DD
= +5 V
±
10%, or
V
SS
= –5 V
±
10%
V
DD
= +15 V
±
10% or
V
SS
= –15 V
±
10%
±
4.5
4.5
±
16.5
28
V
V
mA
mA
mA
mW
%/%
%/%
0.0001 0.01
0.75
0.02
11
0.05
0.01
2
0.1
30
0.15
0.02
DYNAMIC CHARACT ERIST ICS
5, 9, 10
Bandwidth –3 dB
Bandwidth –3 dB
Bandwidth –3 dB
T otal Harmonic Distortion
V
W
Settling T ime
Resistor Noise Voltage
BW_10K
BW_50K
BW_100K
T HD
W
t
S
e
N_WB
R
AB
= 10 k
, Code = 40
H
R
AB
= 50 k
, Code = 40
H
R
AB
= 100 k
, Code = 40
H
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
V
A
= 10 V, V
B
= 0 V,
±
1 LSB Error Band
R
WB
= 25 k
, f = 1 kHz,
RS
= 0
520
125
60
0.005
4
14
kHz
kHz
kHz
%
μ
s
nV
√
Hz
INT ERFACE T IMING CHARACT ERIST ICS (Applies to All Parts [Notes 5, 11])
Input Clock Pulsewidth
Data Setup T ime
Data Hold T ime
CLK to SDO Propagation Delay
12
CS
Setup T ime
CS
High Pulsewidth
Reset Pulsewidth
CLK Rise to
CS
Rise Hold T ime
CS
Rise to Clock Rise Setup
t
CH
, t
CL
t
DS
t
DH
t
PD
t
CSS
t
CSW
t
RS
t
CSH
t
CS1
Clock Level High or Low
120
30
20
10
120
150
120
120
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
L
= 2.2 k
, C
L
< 20 pF
100
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