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参数资料
| 型号： | AD7450ARZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/22页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT DIFF IN 1MSPS 8SOIC |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，单极 |
| 配用： | EVAL-AD7450CBZ-ND - BOARD EVALUATION FOR AD7450 |
–18–
AD7450
POWER VERSUS THROUGHPUT RATE
By using the power-down mode on the AD7450 when not
converting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 24 shows how, as the throughput
rate is reduced, the device remains in its power-down state longer,
and the average power consumption reduces accordingly. It shows
this for both 5 V and 3 V power supplies.
For example, if the AD7450 is operated in continuous sampling
mode with a throughput rate of 100 kSPS and an SCLK of 18 MHz,
and the device is placed in the power-down mode between
conversions, then the power consumption is calculated as follows:
Power dissipation during normal operation = 9 mW max for
VDD = 5 V.
If the power-up time is one dummy cycle, i.e., 1
s, and the
remaining conversion time is another cycle, i.e., 1
s, then the
AD7450 can be said to dissipate 9 mW for 2
s* during each
conversion cycle.
If the throughput rate = 100 kSPS, then the cycle time = 10
s,
and the average power dissipated during each cycle is:
(2/10)
9 mW = 1.8 mW
For the same scenario, if VDD = 3 V, the power dissipation
during normal operation is 3.75 mW max.
The AD7450 can now be said to dissipate 3.75 mW for 2
s*
during each conversion cycle.
The average power dissipated during each cycle with a throughput
rate of 100 kSPS is therefore:
(2/10)
3.75 mW = 0.75 mW
This is how the power numbers in Figure 24 are calculated.
For throughput rates above 320 kSPS, it is recommended that the
serial clock frequency is reduced for optimum power performance.
THROUGHPUT – kSPS
100
0.01
0.1
1
10
0
350
100
150
200
50
250
300
PO
WER
–
mW
VDD = 3V
SCLK = 15MHz
VDD = 5V
SCLK = 18MHz
Figure 24. Power vs. Throughput Rate for
Power-Down Mode
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7450 allows the part to be directly
connected to a range of different microprocessors. This section
explains how to interface the AD7450 with some of the more
common microcontroller and DSP serial interface protocols.
AD7450 to ADSP-21xx
The ADSP-21xx DSPs are interfaced directly to the AD7450
without any glue logic required.
The SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
To implement the power-down mode, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 25. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS
set as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to
CS and, as with all signal processing applica-
tions, equidistant sampling is necessary. However, in this example,
the timer interrupt is used to control the sampling rate of the
ADC and, under certain conditions, equidistant sampling
may not be achieved.
SCLK
SDATA
CS
SCLK
DR
RFS
TFS
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7450*
ADSP-21xx*
Figure 25. Interfacing to the ADSP-21xx
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control word).
The TFS is used to control the RFS and hence the reading of
data. The frequency of the serial clock is set in the SCLKDIV
register. When the instruction to transmit with TFS is given,
(i.e., AX0 = TX0), the state of the SCLK is checked. The DSP
will wait until the SCLK has gone High, Low, and High before
transmission will start. If the timer and SCLK values are chosen
such that the instruction to transmit occurs on or near the rising
edge of SCLK, then the data may be transmitted, or it may wait
until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
then a SCLK of 2 MHz is obtained and eight master clock
periods will elapse for every 1 SCLK period. If the timer regis-
ters are loaded with the value 803, then 100.5 SCLKs will occur
between interrupts and subsequently between transmit instruc-
tions. This situation will result in nonequidistant sampling as
the transmit instruction is occurring on a SCLK edge. If the
number of SCLKs between interrupts is a whole integer figure of
N, then equidistant sampling will be implemented by the DSP.
*This figure assumes a very small time to enter power-down mode. This will
increase as the burst of clocks used to enter the power-down mode is increased.
Rev. A
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