参数资料
型号: AD7466BRM
厂商: ANALOG DEVICES INC
元件分类: ADC
英文描述: 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
中文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封装: MO-187-AA, MSOP-8
文件页数: 1/28页
文件大小: 959K
代理商: AD7466BRM
1.6 V, Micropower
12-, 10-, and 8-Bit ADCs in 6-Lead SOT-23
AD7466/AD7467/AD7468
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Specified for VDD of 1.6 V to 3.6 V
Low power:
0.62 mW typ at 100 kSPS with 3 V supplies
0.48 mW typ at 50 kSPS with 3.6 V supplies
0.12 mW typ at 100 kSPS with 1.6 V supplies
Fast throughput rate: 200 kSPS
Wide input bandwidth:
71 dB SNR at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI-/QSPI-/MICROWIRE-/DSP-compatible
Automatic power-down
Power-down mode: 8 nA typ
6-lead SOT-23 package
8-lead MSOP package
APPLICATIONS
Battery-powered systems
Medical instruments
Remote data acquisition
Isolated data acquisition
GENERAL DESCRIPTION
The AD7466/AD7467/AD74681 are 12-, 10-, and 8-bit, high
speed, low power, successive approximation analog-to-digital
converters (ADCs), respectively. The parts operate from a single
1.6 V to 3.6 V power supply and feature throughput rates up to
200 kSPS with low power dissipation. The parts contain a low
noise, wide bandwidth track-and-hold amplifier, which can
handle input frequencies in excess of 3 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS, and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to VDD. The conversion
rate is determined by the SCLK.
1 Protected by U.S. Patent No. 6,681,332.
FUNCTIONAL BLOCK DIAGRAM
AD7466/AD7467/AD7468
12-/10-/8-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
GND
VDD
VIN
SCLK
SDATA
T/H
02643-001
CS
Figure 1.
PRODUCT HIGHLIGHTS
1.
Specified for supply voltages of 1.6 V to 3.6 V.
2.
12-, 10-, and 8-bit ADCs in SOT-23 packages.
3.
High throughput rate with low power consumption.
Power consumption in normal mode of operation at
100 kSPS and 3 V is 0.9 mW maximum.
4.
Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through
increases in the serial clock speed. Automatic power-down
after conversion allows the average power consumption to
be reduced when in power-down. Current consumption is
0.1 A maximum and 8 nA, typically when in power-down.
5.
Reference derived from the power supply.
6.
No pipeline delay.
7.
The part features a standard successive approximation
ADC with accurate control of conversions via a CS input.
相关PDF资料
PDF描述
AD7466BRT 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7467BRT 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7468BRT 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7466 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7467 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
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