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参数资料
型号： AD7466BRM
厂商： ANALOG DEVICES INC
元件分类： ADC
英文描述： 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封装： MO-187-AA, MSOP-8
文件页数： 2/28页
文件大小： 959K
代理商： AD7466BRM
AD7466/AD7467/AD7468
Rev. B | Page 10 of 28
TIMING EXAMPLES
Figure 3 and Figure 4 show some of the timing parameters from
the Timing Specifications section (Table 4).
Timing Example 1
As shown in Figure 4, fSCLK = 3.4 MHz and a throughput of
100 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 10 s.
Assuming VDD = 1.8 V, tCONVERT = t2 + 15(1/fSCLK) = 55 ns +
4.41 s = 4.46 s, and t8 = 60 ns max, then tQUIET = 5.48 s, which
satisfies the requirement of 10 ns for tQUIET. The part is fully
powered up and the signal is fully acquired at Point A. This
means that the acquisition/power-up time is t2 + 2(1/fSCLK) =
55 ns + 588 ns = 643 ns, satisfying the maximum requirement of
640 ns for the power-up time.
Timing Example 2
The AD7466 can also operate with slower clock frequencies.
As shown in Figure 4, assuming VDD = 1.8 V, fSCLK = 2 MHz,
and a throughput of 50 kSPS gives a cycle time of tCONVERT + t8 +
tQUIET = 20 s. With tCONVERT = t2 + 15(1/fSCLK) = 55 ns + 7.5 s =
7.55 s, and t8 = 60 ns max, this leaves tQUIET to be 12.39 s,
which satisfies the requirement of 10 ns for tQUIET. The part is
fully powered up and the signal is fully acquired at Point A,
which means the acquisition/power-up time is t2 + 2(1/fSCLK) =
55 ns + 1 s = 1.05 s, satisfying the maximum requirement of
640 ns for the power-up time. In this example and with other
slower clock values, the part is fully powered up and the signal
already acquired before the third SCLK falling edge; however,
the track-and-hold does not go into hold mode until that point.
In this example, the part can be powered up and the signal can
be fully acquired at approximately Point B in Figure 4.
SCLK
t2
t3
t4
t7
t5
t8
tCONVERT
tQUIET
DB11
DB10
DB2
DB1
DB0
A
4 LEADING ZEROS
13
14
15
16
t1
THREE-STATE
SDATA
CS
5
4
3
2
1
02643-003
t6
0
Figure 3. AD7466 Serial Interface Timing Diagram Example
SCLK
t2
tCONVERT
B
A
t8
tQUIET
1/THROUGHPUT
AUTOMATIC
POWER-DOWN
TRACK-AND-HOLD IN HOLD
TRACK-AND-HOLD
IN TRACK
ACQUISITION TIME
POINT A: THE PART IF FULLY POWERED UP WITH VIN FULLY ACQUIRED.
1
2
3
CS
4
5
13
14
15
16
02643-004
Figure 4. AD7466 Serial Interface Timing Diagram Example
相关PDF资料
PDF描述
AD7466BRT 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7467BRT 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7468BRT 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7466 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7467 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
相关代理商/技术参数
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AD7466BRMZ-REEL7 功能描述:IC ADC 12BIT 1.6V LP 8-MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:2,500 系列:- 位数:16 采样率（每秒）:15 数据接口:MICROWIRE?，串行，SPI? 转换器数目:1 功率耗散（最大）:480µW 电压电源:单电源 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:38-WFQFN 裸露焊盘 供应商设备封装:38-QFN（5x7） 包装:带卷 (TR) 输入数目和类型:16 个单端，双极；8 个差分，双极 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494
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