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参数资料
| 型号： | AD7467BRT |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封装： | MO-178AB, SOT-23, 6 PIN |
| 文件页数： | 13/24页 |
| 文件大小： | 327K |
| 代理商： | AD7467BRT |
–20–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7466/AD7467/AD7468
For the AD7467, the 14th SCLK falling edge will cause
the SDATA line to go back into three-state and the part
will enter power down. If the rising edge of
CS occurs
before 14 SCLKs have elapsed then the conversion will be
terminated, the SDATA line will go back into three-state
and the AD7467 will enter power down, otherwise
SDATA returns to three-state on the 14th SCLK falling
edge as shown in Figure 15. Fourteen serial clock cycles
are required to perform the conversion process and to
access data from the AD7467.
For the AD7468, the 12th SCLK falling edge will cause
the SDATA line to go back into three-state and the part
will enter power down. If the rising edge of
CS occurs
before 12 SCLKs have elapsed then the conversion will be
terminated, the SDATA line will go back into three-state
and the AD7468 will enter power down, otherwise
SDATA returns to three-state on the 12th SCLK falling
edge as shown in Figure 16. Twelve serial clock cycles are
required to perform the conversion process and to access
data from the AD7468.
CS going low provides the first leading zero to be read in
by the microcontroller or DSP. The remaining data is
Figure 15. AD7467 Serial Interface Timing Diagram
&6
SCLK
1
5
13
SDATA
4 LEADING ZERO’S
3-S TATE
t4
2
34
t3
tQU IET
tCONV ERT
t2
3-STATE
DB9
DB8
DB0
t 6
t7
t8
14
ZERO
ZE RO
Z
B
t
5
then clocked out by subsequent SCLK falling edges be-
ginning with the 2nd leading zero, thus the first clock
falling edge on the serial clock has the first leading zero
provided and also clocks out the second leading zero. For
the AD7466 the final bit in the data transfer is valid on the
16th SCLK falling edge, having being clocked out on the
previous (15th) SCLK falling edge.
In applications with a slow SCLK, it is possible to read in
data on each SCLK rising edge. In that case, the first
falling edge of SCLK will clock out the second leading
zero and it could be read in the first rising edge. However,
the first leading zero that was clocked out when
CS went
low will be missed unless it was not read in the first falling
edge. The 15th falling edge of SCLK will clock out the
last bit and it could be read in the 15th rising SCLK edge.
If
CS goes low just after one the SCLK falling edge has
elapsed,
CS will clock out the first leading zero as before
and it may be read in the SCLK rising edge. The next
SCLK falling edge will clock out the second leading zero
and it could be read in the following rising edge.
&6
t
QU IE T
3- ST A T E
t
5
t
8
B
DB 0
t
7
SCL K
1
S D AT A
4 L EADING Z ER O’S
ZE RO
ZER O
Z
3 -S TAT E
t
4
2
34
t
3
t
CO NV E RT
t2
DB7
t 6
8B IT S OF D A T A
12
11
Figure 16. AD7468 Serial Interface Timing Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| AD7468BRT | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7466 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7467 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7468 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD746A | Dual Precision, 500 ns Settling, BiFET Op Amp |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7467BRT-R | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRT-R2 | 功能描述:IC ADC 10BIT 1.6V LP SOT23-6 RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| AD7467BRT-REEL | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRT-REEL7 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRTZ-R | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
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