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参数资料
| 型号： | AD7467BRT |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封装： | MO-178AB, SOT-23, 6 PIN |
| 文件页数： | 22/24页 |
| 文件大小： | 327K |
| 代理商： | AD7467BRT |
–7–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7466/AD7467/AD7468
Timing Example 1
From Figure 3, having
fSCLK = 3.4MHz and a throughput of 100 KSPS, gives a cycle time of tCONVERT+ t8 + tQUIET =
10
s. With t
CONVERT = t2 + 15(1/fSCLK) = 10 ns + 4.41s = 4.42 s, and t8 = TBD ns min, this leaves tQUIET to be TBD
ns. This TBD ns satisfies the requirement of TBD ns for tQUIET. The part is fully powered up and the signal is fully
acquired at point A, that means the acquisition/power up time is t2 + 2(1/fSCLK) = 10 ns + 0.588 s = 0.59 s satisfying
the maximum requirement of TBD s for the power up time.
Timing Example 2
The AD7466 can also operate with slower clock frequencies. From Figure 3, having
fSCLK = 2MHz and a throughput of
50 KSPS, gives a cycle time of
tCONVERT+ t8 + tQUIET = 20
s. With t
CONVERT = t2 + 15(1/fSCLK) = 10 ns + 7.5s = 7.51
s, and t8 = TBD ns min, this leaves tQUIET to be TBD ns. This TBD ns satisfies the requirement of TBD ns for tQUIET.
The part is fully powered up and the signal is fully acquired at point A, that means the acquisition/power up time is t2 +
2(1/fSCLK) = 10 ns + 1 s = 1.01 s, satisfying the maximum requirement of TBD s for the power up time. As in this
example and with other slower clock values, the part will be fully powered up and the signal already be acquired before
the third SCLK falling edge, however the Track and Hold will not go into hold mode until that point. In this example,
the part may be powered up and the signal may
be fully acquired at approximately point B in Figure 3.
Figure 2. AD7466 Serial InterfaceTiming Diagram
Figures 2 and 3 show some of the timing parameters from the Timing Specifications Section.
&6
SCLK
1
5
13
15
SDATA
4 LEADING ZERO’S
3-STATE
t 4
2
34
16
t5
t3
tQUIET
tCONVERT
t2
3-STATE
DB11
DB10
DB2
DB0
t6
t7
t8
14
ZE RO
ZERO
Z
A
DB1
Figure 3. Serial InterfaceTiming Example
SCLK
1
5
2
34
&6
13
15
16
tQUIET
t2
t 8
14
A
1/THROUGHPUT
tCONVERT
Track/Hold in Track
Automatic Power down
Track/Hold in Hold
PointA: The part is fully poweredupwithVIN fully acquired
B
相关PDF资料 |
PDF描述 |
|---|---|
| AD7468BRT | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7466 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7467 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7468 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD746A | Dual Precision, 500 ns Settling, BiFET Op Amp |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7467BRT-R | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRT-R2 | 功能描述:IC ADC 10BIT 1.6V LP SOT23-6 RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| AD7467BRT-REEL | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRT-REEL7 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRTZ-R | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
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