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参数资料
| 型号： | AD7476AAKSZ-500RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 1MSPS LP SC70-6 |
| 设计资源： | Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165) |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP，SC-88，SOT-363 |
| 供应商设备封装： | SC-70-6 |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个单端，单极 |
| 其它名称： | AD7476AAKSZ-500RL7DKR |
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AD7476A/AD7477A/AD7478A
Rev. F | Page 18 of 28
MODES OF OPERATION
The modes of operation for the AD7476A/AD7477A/AD7478A
are selected by controlling the (logic) state of the CS signal during
a conversion. There are two possible modes of operation: normal
and power-down. The point at which CS is pulled high after the
conversion has been initiated determines whether the AD7476A/
AD7477A/AD7478A enters power-down mode. Similarly, if
already in power-down, CS can control whether the device returns
to normal operation or remains in power-down. These modes of
operation are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for different application
requirements.
NORMAL MODE
This mode is intended for the fastest throughput rate performance.
In normal mode, the user does not have to worry about any
power-up times because AD7476A/AD7477A/AD7478A
remain fully powered at all times. Figure 20 shows the general
diagram of the operation of the AD7476A/AD7477A/AD7478A
in this mode. The conversion is initiated on the falling edge of
CS as described in the Serial Interface section. To ensure that
the part remains fully powered up at all times, CS must remain
low until at least 10 SCLK falling edges have elapsed after the
falling edge of CS. If CS is brought high any time after the 10th
SCLK falling edge but before the end of the tCONVERT, the part
remains powered up, but the conversion is terminated and
SDATA goes back into three-state. For the AD7476A, 16 serial
clock cycles are required to complete the conversion and access
the complete conversion results. For the AD7477A and AD7478A,
a minimum of 14 and 12 serial clock cycles are required to com-
plete the conversion and access the complete conversion results,
respectively. CS can idle high until the next conversion or idle
low until CS returns high sometime prior to the next conversion
(effectively idling CS low). Once a data transfer is complete
(SDATA has returned to three-state), another conversion can be
initiated after the quiet time, tQUIET, has elapsed by bringing CS
low again.
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions is performed
at a high throughput rate and the ADC is then powered down
for a relatively long duration between these bursts of several
conversions. When the AD7476A/AD7477A/AD7478A are in
power-down, all analog circuitry is powered down. To enter
power-down, the conversion process must be interrupted by
bringing CS high anywhere after the second falling edge of SCLK
and before the 10th falling edge of SCLK, as shown in Figure 22.
Once CS has been brought high in this window of SCLKs, the
part enters power-down, the conversion that was initiated by
the falling edge of CS is terminated, and SDATA goes back into
three-state. If CS is brought high before the second SCLK falling
edge, the part remains in normal mode and does not power
down. This avoids accidental power-down due to glitches on the
CS line. In order to exit this mode of operation and power up
the AD7476A/AD7477A/AD7478A again, a dummy conversion
is performed. On the falling edge of CS, the device begins to
power up and continues to power up as long as CS is held low
until after the falling edge of the 10th SCLK. The device is fully
powered up once 16 SCLKs have elapsed, and valid data results
from the next conversion, as shown in Figure 24. If CS is
brought high before the 10th falling edge of SCLK, then the
AD7476A/AD7477A/AD7478A go back into power-down. This
avoids accidental power-up due to glitches on the CS line or an
inadvertent burst of eight SCLK cycles while CS is low.
Although the device can begin to power up on the falling edge
of CS, it powers down again on the rising edge of CS as long as it
occurs before the 10th SCLK falling edge.
POWER-UP TIME
The power-up time of the AD7476A/AD7477A/AD7478A is
1 s, meaning that with any frequency of SCLK up to 20 MHz,
one dummy cycle is always sufficient to allow the device to
power up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
time, tQUIET, must still be allowed from the point where the bus
goes back into three-state after the dummy conversion to the
next falling edge of CS. When running at a 1 MSPS throughput
rate, the AD7476A/AD7477A/AD7478A power up and acquire
a signal within 0.5 LSB in one dummy cycle, that is, 1 s.
When powering up from the power-down mode with a dummy
cycle, as in Figure 22, the track-and-hold that was in hold mode
while the part was powered down returns to track mode after
the first SCLK edge the part receives after the falling edge of CS.
This is shown as Point A in Figure 22. Although at any SCLK
frequency, one dummy cycle is sufficient to power up the device
and acquire VIN, it does not necessarily mean that a full dummy
cycle of 16 SCLKs must always elapse to power up the device
and acquire VIN fully; 1 s is sufficient to power up the device
and acquire the input signal. If, for example, a 5 MHz SCLK
frequency is applied to the ADC, the cycle time becomes 3.2 s.
In one dummy cycle, 3.2 s, the part powers up and VIN
acquires fully. However, after 1 s with a 5 MHz SCLK, only five
SCLK cycles would have elapsed. At this stage, the ADC would
fully power up and acquire the signal. In this case, the CS can be
brought high after the 10th SCLK falling edge and brought low
again after a time, tQUIET, to initiate the conversion.
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相关代理商/技术参数 |
参数描述 |
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| AD7476AAKSZ-REEL | 功能描述:IC ADC 12BIT 1MSPS LP SC70-6 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7476AAKSZ-REEL7 | 功能描述:IC ADC 12BIT 1MSPS LP SC70-6 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7476ABKS-500RL7 | 制造商:Rochester Electronics LLC 功能描述:12-BIT LOW POWER ADC SC70 PKS I.C. - Bulk 制造商:Analog Devices 功能描述: |
| AD7476ABKS-REEL | 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 12-BIT SERL 6PIN SC-70 - Tape and Reel |
| AD7476ABKS-REEL7 | 制造商:Rochester Electronics LLC 功能描述:12-BIT LOW POWER ADC IN SC70 PACKAGE - Tape and Reel 制造商:Analog Devices 功能描述: |
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