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| 型号： | AD7476AYKSZ-500RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 1MSPS SC70-6 |
| 设计资源： | Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165) |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP，SC-88，SOT-363 |
| 供应商设备封装： | SC-70-6 |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个单端，单极 |
| 其它名称： | AD7476AYKSZ-500RL7DKR AD7476AYKSZ500RL7DKR AD7476AYKSZ500RL7DKR-ND |
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AD7476A/AD7477A/AD7478A
Rev. F | Page 8 of 28
TIMING SPECIFICATIONS
Table 4.
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK2
10
kHz min3
A, B grades
20
kHz min3
Y grade
20
MHz max
tCONVERT
16 × tSCLK
AD7476A
14 × tSCLK
AD7477A
12 × tSCLK
AD7478A
tQUIET
50
ns min
Minimum quiet time required between bus relinquish
and start of next conversion
t1
10
ns min
Minimum CS pulse width
t2
10
ns min
CS to SCLK setup time
t34
22
ns max
Delay from CS until SDATA three-state disabled
t44
40
ns max
Data access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK low pulse width
t6
0.4 tSCLK
ns min
SCLK high pulse width
t75
SCLK to data valid hold time
10
ns min
VDD ≤ 3.3 V
9.5
ns min
3.3 V < VDD ≤ 3.6 V
7
ns min
VDD > 3.6 V
t86
36
ns max
SCLK falling edge to SDATA high impedance
t7 values also apply to t8 minimum values
ns min
SCLK falling edge to SDATA high impedance
tPOWER-UP7
1
μs max
Power-up time from full power-down
1
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Minimum fSCLK at which specifications are guaranteed.
4
Measured with the load circuit shown in Figure 2, and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V, and
0.8 V or 2.0 V for VDD > 2.35 V.
5
Measured with a 50 pF load capacitor.
6
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. Therefore, the time, t8, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
7
See the Power-Up Time section.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7476AYKSZ-500RL73 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70 |
| AD7476AYKSZ-REEL7 | 功能描述:IC ADC 12BIT 1MSPS SC70-6 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7476AYKSZ-REEL73 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70 |
| AD7476AYRM | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 8-Pin MSOP 制造商:Rochester Electronics LLC 功能描述:12-BIT LOW VOLTAGE, LOW POWER ADC I.C. - Bulk |
| AD7476AYRM-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 8-Pin MSOP T/R 制造商:Rochester Electronics LLC 功能描述:12-BIT LOW VOLTAGE, LOW POWER ADC I.C. - Tape and Reel |
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