参数资料
型号: AD7476AYKSZ-REEL7
厂商: Analog Devices Inc
文件页数: 10/29页
文件大小: 0K
描述: IC ADC 12BIT 1MSPS SC70-6
设计资源: Output Channel Monitoring Using AD5380 (CN0008)
AD5382 Channel Monitor Function (CN0012)
AD5381 Channel Monitor Function (CN0013)
AD5383 Channel Monitor Function (CN0015)
AD5390/91/92 Channel Monitor Function (CN0030)
Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
标准包装: 3,000
位数: 12
采样率(每秒): 1M
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 17.5mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-TSSOP,SC-88,SOT-363
供应商设备封装: SC-70-6
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极
配用: EVAL-AD7476ACBZ-ND - BOARD EVALUATION FOR AD7476A
AD7476A/AD7477A/AD7478A
Rev. F | Page 17 of 28
Table 8 provides typical performance data with various op amps
used as the input buffer for a 100 kHz input tone at room
temperature under the same setup conditions.
Table 8. AD7476A Typical Performance with Various Input
Buffers, VDD = 3 V
Op Amp in the Input Buffer
AD7476A SNR Performance (dB)
72.3
72.5
71.4
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source imped-
ance depends on the amount of total harmonic distortion (THD)
that can be tolerated. The THD increases as the source impedance
increases, degrading the performance (see Figure 13).
DIGITAL INPUTS
The digital inputs applied to the AD7476A/AD7477A/AD7478A
are not limited by the maximum ratings that limit the analog
input. Instead, the digital inputs applied can reach 7 V and are
not restricted by the VDD + 0.3 V limit as on the analog input.
For example, if operating the AD7476A/AD7477A/AD7478A
with a VDD of 3 V, use 5 V logic levels on the digital inputs.
However, note that the data output on SDATA still has 3 V logic
levels when VDD = 3 V. Another advantage of SCLK and CS not
being restricted by the VDD + 0.3 V limit is that power supply
sequencing issues are avoided. If CS or SCLK are applied before
VDD, there is no risk of latch-up as there would be on the analog
input if a signal greater than 0.3 V were applied prior to VDD.
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