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参数资料
| 型号： | AD7478AAKSZ-REEL |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:3; Connector Shell Size:28; Connecting Termination:Solder; Circular Shell Style:Square Flange Receptacle; Body Style:Straight |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封装： | ROHS COMPLIANT, MO-203AB, SC-70, 6 PIN |
| 文件页数： | 20/24页 |
| 文件大小： | 580K |
| 代理商： | AD7478AAKSZ-REEL |
REV. C
–20–
AD7476A/AD7477A/AD7478A
To summarize, the values in the SPC register are
FO = 0
FSM = 1
MCM = 1
TXM = 1
The format bit, FO, may be set to 1 to set the word length to
eight bits in order to implement the power-down mode on the
AD7476A/AD7477A/AD7478A.
The connection diagram is shown in Figure 17. It should be noted
that for signal processing applications, it is imperative that the
frame synchronization signal from the TMS320C541 provides
equidistant sampling.
AD7476A/
AD7477A/
AD7478A
*
SCLK
SDATA
CS
CLKX
CLKR
FSX
FSR
TMS320C541
*
*
ADDITIONAL PINS OMITTED FOR CLARITY.
DR
Figure 17. Interfacing to the TMS320C541
AD7476A/AD7477A/AD7478A to ADSP-218x
The ADSP-218x family of DSPs are interfaced directly to the
AD7476A/AD7477A/AD7478A without any glue logic required.
The SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0, Sets Up RFS as an Input
ITFS = 1, Sets Up TFS as an Output
SLEN = 1111, 16 Bits for the AD7476A
SLEN = 1101, 14 Bits for the AD7477A
SLEN = 1011, 12 Bits for the AD7478A
To implement the power-down mode, SLEN should be set to
0111 to issue an 8-bit SCLK burst. The connection diagram is
shown in Figure 18. The ADSP-218x has the TFS and RFS of
the SPORT tied together, with TFS set as an output and RFS
set as an input. The DSP operates in alternate framing mode, and
the SPORT control register is set up as described. The frame
synchronization signal generated on the TFS is tied to
CS
, and,
as with all signal processing applications, equidistant sampling is
necessary. However, in this example, the timer interrupt is used
to control the sampling rate of the ADC and, under certain
conditions, equidistant sampling may not be achieved.
The timer registers, for example, are loaded with a value that will
provide an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT
(ADC control word). The TFS is used to control the RFS and
thus the reading of data. The frequency of the serial clock is set in
the SCLKDIV register. When the instruction to transmit with
TFS is given, i.e., TX0 = AX0, the state of the SCLK is checked.
The DSP will wait until the SCLK has gone high, low, and high
before transmission will start. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, the data may be transmitted or it may
wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
an SCLK of 2 MHz is obtained and eight master clock periods will
elapse for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs will occur between interrupts and
subsequently between transmit instructions. This situation will result
in nonequidistant sampling as the transmit instruction is occurring
on an SCLK edge. If the number of SCLKs between interrupts is a
whole integer figure of N, equidistant sampling will be implemented
by the DSP.
AD7476A/
AD7477A/
AD7478A
*
SCLK
SDATA
CS
SCLK
DR
RFS
TFS
ADSP-218x
*
*
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 18. Interfacing to the ADSP-218x
AD7476A/AD7477A/AD7478A to DSP563xx Interface
The connection diagram in Figure 19 shows how the AD7476A/
AD7477A/AD7478A can be connected to the SSI (synchronous
serial interface) of the DSP563xx family of DSPs from Motorola.
The SSI is operated in synchronous and normal mode (SYN = 1
and MOD = 0 in Control Register B, CRB) with internally gener-
ated word frame sync for both Tx and Rx (Bits FSL1 = 0 and
FSL0 = 0 in CRB). Set the word length in Control Register A
(CRA) to 16 by setting Bits WL2 = 0, WL1 = 1, and WL0 = 0
for the AD7476A. The word length for the AD7478A can be set
to 12 bits (WL2 = 0, WL1 = 0, and WL0 = 1). This DSP does not
offer the option for a 14-bit word length, so the AD7477A word
length will be set up to 16 bits, the same as the AD7476A. For the
AD7477A, the conversion process will use 16 SCLK cycles,
with the last two clock periods clocking out two trailing zeros to
fill the 16-bit word.
To implement the power-down mode on the AD7476A/AD7477A/
AD7478A, the word length can be changed to eight bits by setting
Bits WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in
the CRB register can be set to 1, meaning the frame goes low
and a conversion starts. Likewise, by means of the Bits SCD2,
SCKD, and SHFD in the CRB register, it will be established that
the Pins SC2 (the frame sync signal) and SCK in the serial port
will be configured as outputs and the MSB will be shifted first.
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| AD7478AAKSZ-REEL3 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70 |
| AD7478AAKSZ-REEL7 | 功能描述:IC ADC 8BIT 1MSPS SC70-6 T/R RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:2,500 系列:- 位数:16 采样率（每秒）:15 数据接口:MICROWIRE?，串行，SPI? 转换器数目:1 功率耗散（最大）:480µW 电压电源:单电源 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:38-WFQFN 裸露焊盘 供应商设备封装:38-QFN（5x7） 包装:带卷 (TR) 输入数目和类型:16 个单端，双极；8 个差分，双极 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD7478AAKSZ-REEL73 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70 |
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