参数资料
| 型号： | AD7485BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/15页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SAR 1MSPS 48-LQFP |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 1M |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 80mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个单端，单极 |
REV.
AD7485
–3–
Parameter
Specification
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
5V
±5%
VDRIVE
2.7
V min
5.25
V max
IDD
Normal Mode (Static)
mA max
Normal Mode (Operational)
mA max
NAP Mode
0.6
mA max
STANDBY Mode
8
2
A max
0.5
A typ
Power Dissipation
Normal Mode (Operational)
mW max
NAP Mode
3
mW max
STANDBY Mode
8
10
W max
NOTES
1Temperature ranges as follows: –40
°C to +85°C.
2SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.
3See Typical Performance Characteristics section for analog input circuits used.
4See Terminology.
5Sample tested @ 25
°C to ensure compliance.
6Current drawn from external reference during conversion.
7I
LOAD = 200
A.
8Digital input levels at GND or V
DRIVE.
Specifications subject to change without notice.
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
fMCLK
0.01
25
MHz
MCLK Period
t1
40
100000
ns
Conversion Time
t2
t1
24
ns
CONVST Low Period (Mode 1)2
t3
t1
22
ns
CONVST High Period (Mode 1)2
t4
10
ns
MCLK High Period
t5
0.4
t1
0.6
t1
ns
MCLK Low Period
t6
0.4
t1
0.6
t1
ns
CONVST Falling Edge to MCLK Rising Edge
t7
7ns
MCLK Rising Edge to MSB Valid
t8
15
ns
Data Valid before SCO Falling Edge
t9
10
ns
Data Valid after SCO Falling Edge
t10
20
ns
CONVST Rising Edge to SDO Three-State
t11
6ns
CONVST Low Period (Mode 2)2
t12
10
t1
2ns
CONVST High Period (Mode 2)3
t13
10
ns
CONVST Falling Edge to TFS Falling Edge
t14
10
ns
TFS Falling Edge to MSB Valid
t15
30
ns
TFS Rising Edge to SDO Three-State
t16
8ns
TFS Low Period4
t17
t1
22
ns
TFS High Period4
t18
10
ns
MCLK Fall Time
t19
525
ns
MCLK Rise Time
t20
525
ns
MCLK – SCO Delay
t21
625
ns
NOTES
1All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.
2
CONVST idling high. See Serial Interface section for further details.
3
CONVST idling low. See Serial Interface section for further details.
4
TFS can also be tied low in this mode.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1 (VDD = 5 V
5%, AGND = DGND = 0 V, VREF = External; all specifications TMIN to TMAX and
valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted.)
13
17
85
A
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