参数资料
型号: AD7537KRZ
厂商: Analog Devices Inc
文件页数: 7/10页
文件大小: 0K
描述: IC DAC 12BIT DUAL MULT 24SOIC
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 31
设置时间: 250µs
位数: 12
数据接口: 并联
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 24mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 管件
输出数目和类型: 2 电流,单极;2 电流,双极
采样率(每秒): 667k
AD7537
REV.
–6–
SEPARATE AGND PINS
The DACs in the AD7537 have separate AGND lines taken to
pins AGNDA and AGNDB on the package. This increases the
applications versatility of the part. Figure 6 is an example of
this. DAC A is connected in standard fashion as a program-
mable attenuator. AGNDA is at ground potential. DAC B is op-
erating with AGND B biased to +5 V by the AD584. This gives
an output range of +5 V to +10 V.
Figure 6. AD7537 DACs Used in Different Modes
PROGRAMMABLE OSCILLATOR
Figure 7 shows a conventional state variable oscillator in which
the AD7537 controls the programmable integrators. The fre-
quency of oscillation is given by:
f
=
1
2
π
R
6
R
5
×
1
C
1
×C2× REQ1× REQ2
where REQ1 and REQ2 are the equivalent resistances of the
DACs. The same digital code is loaded into both DACs.
If C1 = C2 and R5 = R6, the expression reduces to
f
=
1
2
π
×
1
C
1
REQ1 × REQ2
Since R
EQ
=
2n
× R
LAD
N
, (RLAD = DAC ladder resistance).
f
=
1
2
π
×
1
C
(N /2n )2
RLAD1 × RLAD2
=
1
2
π
×
D
C
1
RLAD1 × RLAD2
D
=
N
2n
=
1
2
π
×
D
C
× R
LAD m
where m is the DAC ladder resistance mismatch ratio, typically
1.005.
With the values shown in Figure 7, the output frequency varies
from 0 Hz to 1.38 kHz. The amplitude of the output signal at
the A3 output is 10 V peak-to-peak and is constant over the
entire frequency span.
Figure 7. Programmable State Variable Oscillator
A
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