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参数资料
| 型号： | LTC4245IG#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 21/36页 |
| 文件大小： | 431K |
| 描述： | IC CNTRLR HOT SWAP 36-SSOP |
| 标准包装： | 1,000 |
| 类型： | 热交换控制器 |
| 应用： | CompactPCI? |
| 内部开关： | 无 |
| 电源电压： | 3.3V，5V，12V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 36-SSOP |
| 包装： | 带卷 (TR) |
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LTC4245
21
4245fa
Resetting Faults
The two fault registers E and F can be reset in any of the
following ways:
1. Writing zeros to the registers using the I
2
C bus.
2. Taking the ON pin high to low resets both
registers.
3. INTV
CC
falling below its undervoltage lockout
threshold.
4. Bringing BD_SEL# from high to low clears all fault bits
except bit F6. Bit F6, which indicates a BD_SEL#
change of state, will be set.
Note that faults that are still present cannot be cleared.
Overcurrent and PGI faults are continuously set during their
cool-down timing cycles and hence cannot be reset for
that duration. The fault registers will not be cleared when
auto-retrying. When autoretry is disabled the existence of
an undervoltage (E0 to E3), overcurrent (E4 to E7) or PGI
(F4) fault keeps the switches off. As soon as the fault is
cleared, the switches will turn on.
Precharge
The PRECHARGE pin provides a 1V voltage (using a divided
down 3V
IN
as the reference) that is used to bias the CPCI
bus connector pins during board insertion and extraction.
The pin can source 70mA without losing regulation. An
external 18?resistor from this pin to ground provides the
current sink capability. At least one long 3.3V connector
pin must be connected to 3V
IN
to provide early power to
the precharge circuit.
Resistors are used to connect the 1V bias voltage to the
CPCI bus signals. For 5V signaling this resistance must
be greater than 10k?- 5% (Figure 1). For 3.3V signaling
if the leakage current on the I/O line is greater than 2礎,
the precharge resistors need to be disconnected during
normal operation. Figure 10 shows a circuit that uses a
bus switch to accomplish this. The connection is made
when the voltage on the BD_SEL# pin is pulled up to 5V,
which occurs just after the long pins have made contact.
The resistors are disconnected when the short BD_SEL#
connector pin makes contact and the BD_SEL# voltage
drops below 4.4V thus causing
?/DIV>
O
?/DIV>
E to be pulled high by
APPLICATIO S I FOR ATIO
U
U
Figure 10. Precharge Bus Switch Application Circuit for 3.3V and Universal Hot Swap Boards
5V
IN
C5
10nF
PER PIN
36
10
23
Z2: SMAJ5.0A
*ADDITIONAL DETAILS OMITTED FOR CLARITY
DATA BUS
I/O
4245 F10
9
R9
18& 5%
R20
10&
5%
R22
10k
5%
R23
10k
5%
I/O
R21
10&
5%
R18
2.74&
PCI
BRIDGE
CHIP
5V
LONG 5V
BD_SEL#
GROUND
I/O PIN 1
I/O PIN 128
Z2
C4
10nF
PER PIN
UP TO 128 I/O LINES
C10
0.1礔
100&
Q5
MMBT3906
R24
51k 5%
R25
75k
5%
BUS SWITCH
V
DD
OE
OUT
OUT
IN
CARD
CONNECTOR
BACKPLANE
CONNECTOR
R17
1.2k
5%
GND
5V
IN
BD_SEL#
LTC4245G*
PRECHARGE
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