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| 型号： | AD7643BCPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT DIFF W/REF 48-LFCSP |
| 产品培训模块： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 标准包装： | 2,500 |
| 系列： | PulSAR® |
| 位数： | 18 |
| 采样率（每秒）： | 1.25M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 80mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
| 配用： | EVAL-AD7643CBZ-ND - BOARD EVALUATION FOR AD7643 |
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AD7643
Rev. 0 | Page 22 of 28
16-Bit and 8-Bit Interface (Master or Slave)
In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2)
interfaces, the A0/A1 pins allow a glueless interface to a 16- or
8-bit bus, as shown in Figure 35. By connecting A0/A1 to an
address line(s), the data can be read in two words for a 16-bit
interface, or three bytes for an 8-bit interface. This interface can
be used in both master and slave parallel reading modes. Refer
to Table 7 for the full details of the interface.
CS, RD
A1
D[17:2]
HI-Z
HIGH
WORD
LOW
WORD
HI-Z
t12
t13
HIGH
BYTE
A0
MID
BYTE
LOW
BYTE
D[17:10]
t12
HI-Z
t12
06
02
4-
0
35
Figure 35. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7643 is configured to use the serial interface when
MODE[1:0] = 3. The AD7643 outputs 18 bits of data, MSB first,
on the SDOUT pin. This data is synchronized with the 18 clock
pulses provided on the SCLK pin. The output data is valid on
both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7643 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7643 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted. Depending on the read during
convert input, RDC/SDIN, the data can be read after each
conversion or during the following conversion. Figure 36 and
Figure 37 show detailed timing diagrams of these two modes.
Usually, because the AD7643 is used with a fast throughput, the
master read during conversion mode is the most recommended
serial mode. In this mode, the serial clock and data toggle at
appropriate instants, minimizing potential feedthrough between
digital activity and critical conversion decisions. In this mode,
the SCLK period changes because the LSBs require more time
to settle and the SCLK is derived from the SAR conversion cycle.
In read after conversion mode, it should be noted that unlike
other modes, the BUSY signal returns low after the 18 data bits
are pulsed out and not at the end of the conversion phase,
resulting in a longer BUSY width. As a result, the maximum
throughput cannot be achieved in this mode.
In addition, in read after convert mode, the SCLK frequency
can be slowed down to accommodate different hosts using the
DIVSCLK[1:0] inputs. Refer to Table 4 for the SCLK timing
details when using these inputs.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7643BSTZ | 功能描述:IC ADC 18BIT DIFFER W/REF 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| AD7643BSTZRL | 功能描述:IC ADC 18BIT DIFFER W/REF 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD7645AQ | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645BQ | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645CQ | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
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