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| 型号： | AD7643BCPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT DIFF W/REF 48-LFCSP |
| 产品培训模块： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 标准包装： | 2,500 |
| 系列： | PulSAR® |
| 位数： | 18 |
| 采样率（每秒）： | 1.25M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 80mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
| 配用： | EVAL-AD7643CBZ-ND - BOARD EVALUATION FOR AD7643 |
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AD7643
Rev. 0 | Page 9 of 28
Pin
No.
Mnemonic
Type1
Description
14
D7
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus.
or INVSYNC
When MODE[1:0] = 3 (serial mode), invert sync select. In serial master mode (EXT/INT = low), this
input is used to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15
D8
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus.
or INVSCLK
When MODE[1:0] = 3 (serial mode), invert SCLK select. In all serial modes, this input is used to
invert the SCLK signal.
16
D9
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus.
or RDC
When MODE[1:0] = 3 (serial mode), read during convert. When using serial master mode
(EXT/INT = low), RDC is used to select the read mode.
When RDC = high, the previous conversion result is output on SDOUT during conversion and
the period of SCLK changes (see the Master Serial Interface section).
When RDC = low (read after convert), the current result can be output on SDOUT only when
the conversion is complete.
or SDIN
When MODE[1:0] = 3 (serial mode), serial data in. When using serial slave mode (EXT/INT = high),
SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs
onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK
periods after the initiation of the read sequence.
17
OGND
P
Input/Output Interface Digital Power Ground.
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the
host interface (2.5 V or 3 V).
19
DVDD
P
Digital Power. Nominally at 2.5 V.
20
DGND
P
Digital Power Ground.
21
D10
DO
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus.
or SDOUT
When MODE[1:0] = 3 (serial mode), serial data output. In serial mode, this pin is used as the serial
data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7643
provides the conversion result, MSB first, from its internal shift register. The data format is
determined by the logic level of OB/2C.
In master mode, EXT/INT = low. SDOUT is valid on both edges of SCLK.
In slave mode, EXT/INT = high:
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
22
D11
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.
or SCLK
When MODE[1:0] = 3 (serial mode), serial clock. In all serial modes, this pin is used as the serial
data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge
where the data SDOUT is updated depends on the logic state of the INVSCLK pin.
23
D12
DO
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.
or SYNC
When MODE[1:0] = 3 (serial mode), frame synchronization. In serial master mode (EXT/INT= low),
this output is used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high
while SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low
while SDOUT output is valid.
24
D13
DO
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
or RDERROR
When MODE[1:0] = 3 (serial mode), read error. In serial slave mode (EXT/INT = high), this output
is used as an incomplete read error flag. If a data read is started and not completed when the
current conversion is complete, the current data is lost and RDERROR is pulsed high.
25 to
28
D[14:17]
DO
Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of
the interface mode.
29
BUSY
DO
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.
30
DGND
P
Digital Power Ground.
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相关代理商/技术参数 |
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| AD7643BSTZ | 功能描述:IC ADC 18BIT DIFFER W/REF 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| AD7643BSTZRL | 功能描述:IC ADC 18BIT DIFFER W/REF 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD7645AQ | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645BQ | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645CQ | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
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