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参数资料
| 型号： | AD7663ASTZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT CMOS 48-LQFP T/R |
| 产品培训模块： | Power Line Monitoring |
| 标准包装： | 2,000 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 41mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；4 个单端，双极 |
| 配用： | EVAL-AD7663CBZ-ND - BOARD EVALUATION FOR AD7663 |
REV. B
AD7663
–19–
CS
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
t35
t36 t37
t31
t32
t16
t33
t34
X15
X14
X
12
3
14
15
16
17
18
EXT/
INT = 1
RD = 0
Figure 19. Slave Serial Data Timing for Reading (Read after Convert)
SLAVE SERIAL INTERFACE
External Clock
The AD7663 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
INT pin is
held HIGH. In this mode, several methods can be used to read
the data. The external serial clock is gated by
CS and the data
are output when both
CS and RD are LOW. Thus, depending
on
CS, the data can be read after each conversion or during the
following conversion. The external clock can be either a continu-
ous or discontinuous clock. A discontinuous clock can be either
normally high or normally low when inactive. Figures 19 and 21
show the detailed timing diagrams of these methods.
While the AD7663 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is par-
ticularly important during the second half of the conversion
phase because the AD7663 provides error correction circuitry
that can correct for an improper bit decision made during the first
half of the conversion phase. For this reason, it is recommended
that when an external clock is being provided, it is a discontinuous
clock that is toggling only when BUSY is LOW or, more
importantly, that does not transition during the latter half of
BUSY HIGH.
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
LOW, the result of this conversion can be read while both
CS and
RD are LOW. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both the rising and falling edge of the clock.
Among the advantages of this method, the conversion performance
is not degraded because there are no voltage transients on the
digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7663 provides a “daisy-chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when desired as, for instance, in
isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 20. Simultaneous sampling is possible by using a com-
mon
CNVST signal. It should be noted that the RDC/SDIN
input is latched on the opposite edge of SCLK of the one used
to shift out the data on SDOUT. Therefore, the MSB of the
“upstream” converter just follows the LSB of the “downstream”
converter on the next SCLK cycle.
CNVST
CS
SCLK
SDOUT
RDC/SDIN
BUSY
DATA
OUT
AD7663
#1
(DOWNSTREAM)
BUSY
OUT
CNVST
CS
SCLK
AD7663
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CS IN
CNVST IN
Figure 20. Two AD7663s in a Daisy-Chain Configuration
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7663CB1 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 250 kSPS CMOS ADC |
| AD7664 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 570 kSPS CMOS ADC |
| AD7664ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 570ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:ADC SGL SAR 570KSPS 16BIT PARALLEL/SERL 48LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述:16-BIT, 500KSPS CMOS ADC - Bulk |
| AD7664ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 570ksps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R |
| AD7664ACPZ | 功能描述:IC ADC 16BIT UNIPOLAR 48-LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
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