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参数资料
| 型号： | AD7687BRMZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 250KSPS 10MSOP |
| 标准包装： | 1,000 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 250k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 12.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
| 配用： | EVAL-AD7687CBZ-ND - BOARD EVALUATION FOR AD7687 |
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AD7687
Data Sheet
Rev. B | Page 20 of 28
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is usually used when multiple AD7687s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7687s is shown in
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7687 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing low its SDI input, which consequently outputs the
MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the 16th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7687 can be read.
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
02972-
038
CNV
SCK
SDO
SDI
AD7687
CNV
SCK
SDO
SDI
AD7687
Figure 39. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
SDO
D15
D14
D13
D1
D0
tDIS
SCK
12
3
30
31
32
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
14
15
tSCK
tSCKL
tSCKH
D0
D15
D14
17
18
16
SDI(CS2)
02972-
039
Figure 40. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing
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