参数资料
型号: AD7688BCPZRL7
厂商: Analog Devices Inc
文件页数: 14/28页
文件大小: 0K
描述: IC ADC 16BIT SAR 500KSPS 10LFCSP
标准包装: 1
系列: PulSAR®
位数: 16
采样率(每秒): 500k
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 21.5mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘,CSP
供应商设备封装: 10-LFCSP-WD(3x3)
包装: 标准包装
输入数目和类型: 2 个单端,单极;2 个单端,双极;1 个差分,单极;1 个差分,双极
其它名称: AD7688BCPZRL7DKR
AD7688
Rev. A | Page 21 of 28
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7688s on a 3-
wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7688s is shown in
Figure 42 and the corresponding timing is given in Figure 43.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7688 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently more AD7688s in the chain, provided
the digital host has an acceptable hold time. The maximum
conversion rate may be reduced due to the total readback time.
For instance, with a 3 ns digital host set-up time and 3 V
interface, up to four AD7688s running at a conversion rate of
360 kSPS can be daisy-chained on a 3-wire port.
CLK
CONVERT
DATA IN
DIGITAL HOST
02973-
041
CNV
SCK
SDO
SDI
AD7688
B
CNV
SCK
SDO
SDI
AD7688
A
Figure 42. Chain Mode, No BUSY Indicator Connection Diagram
SDOA = SDIB
DA15
DA14
DA13
SCK
1
2
3
30
31
32
tSSDISCK
tHSDISC
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
14
15
tSCK
tSCKL
tSCKH
DA0
17
18
16
SDIA = 0
SDOB
DB15
DB14
DB13
DA1
DB1DB0DA15
DA14
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
02973-
042
Figure 43. Chain Mode, No BUSY Indicator Serial Interface Timing
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