参数资料
型号: AD7693BCPZRL7
厂商: Analog Devices Inc
文件页数: 11/24页
文件大小: 0K
描述: IC ADC 16BIT 500KSPS 10-LFCSP
标准包装: 1
系列: PulSAR®
位数: 16
采样率(每秒): 500k
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 21.5mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘,CSP
供应商设备封装: 10-LFCSP-WD(3x3)
包装: 标准包装
输入数目和类型: 1 个差分,双极
其它名称: AD7693BCPZRL7DKR
AD7693
Rev. A | Page 19 of 24
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7693s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7693s is shown in
Figure 38, and the corresponding timing is given in Figure 39.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7693 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge or when SDI goes high (whichever occurs
first), SDO returns to high impedance and another AD7693 can
be read.
DATA IN
CLK
CS1
CONVERT
CS2
CNV
SCK
SDO
SDI
CNV
SCK
SDO
SDI
AD7693
0
63
94
-0
37
DIGITAL HOST
Figure 38. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
SDO
D15
D14
D13
D1
D0
tDIS
SCK
12
3
30
31
32
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
14
15
tSCK
tSCKL
tSCKH
D0
D16
D15
17
18
16
SDI(CS2)
0
63
94
-03
8
Figure 39. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
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