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| 型号： | AD7706BRU-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 3CH 16-TSSOP T/R |
| 标准包装： | 1,000 |
| 位数： | 16 |
| 采样率（每秒）： | 500 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 3 个伪差分，单极; 3 个伪差分，双极 |
| 配用： | EVAL-AD7706EBZ-ND - BOARD EVALUATION FOR AD7706 |
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AD7705/AD7706
Rev. C | Page 19 of 44
CLOCK REGISTER (RS2, RS1, RS0 = 0, 1, 0); POWER-ON/RESET STATUS: 05 HEXADECIMAL
The clock register is an 8-bit register from which data can be read or to which data can be written.
outlines the bit designations for the clock register.
Table 18. Clock Register
ZERO (0)
CLKDIS (0)
CLKDIV (0)
CLK (1)
FS1 (0)
FS0 (1)
Table 19. Clock Register Description
Register
Description
ZERO
Zero. A zero must be written to these bits to ensure correct operation of the AD7705/AD7706. Failure to do so might result in
unspecified operation of the device.
CLKDIS
Master Clock Disable Bit. Logic 1 in this bit disables the master clock, preventing it from appearing at the MCLK OUT pin. When
disabled, the MCLK OUT pin is forced low. This feature allows the user the flexibility of either using the MCLK OUT as a clock
source for other devices in the system, or turning off the MCLK OUT as a power-saving feature. When using an external master
clock on the MCLK IN pin, the AD7705/AD7706 continue to have internal clocks and convert normally with the CLKDIS bit
active. When using a crystal oscillator or ceramic resonator across Pin MCLK IN and Pin MCLK OUT, the AD7705/AD7706 clocks
are stopped, and no conversions take place when the CLKDIS bit is active.
CLKDIV
Clock Divider Bit. With this bit at Logic 1, the clock frequency appearing at the MCLK IN pin is divided by 2 before being used
internally by the AD7705/AD7706. For example, when this bit is set to Logic 1, the user can operate with a 4.9152 MHz crystal
between Pin MCLK IN and Pin MCLK OUT, and internally the part operates with the specified 2.4576 MHz. With this bit at
Logic 0, the clock frequency appearing at the MCLK IN pin is the frequency used internally by the part.
CLK
Clock Bit. This bit should be set in accordance with the operating frequency of the AD7705/AD7706. If the device has a master
clock frequency of 2.4576 MHz (CLKDIV = 0) or 4.9152 MHz (CLKDIV = 1), this bit should be set to Logic 1. If the device has a
master clock frequency of 1 MHz (CLKDIV = 0) or 2 MHz (CLKDIV = 1), this bit should be set to Logic 0. This bit sets up the
appropriate scaling currents for a given operating frequency and, together with FS1 and FS0, chooses the output update rate
for the device. If this bit is not set correctly for the master clock frequency of the device, the AD7705/AD7706 might not
operate to specification.
FS1, FS0
Filter Selection Bits. Along with the CLK bit, FS1 and FS0 determine the output update rate, the filter’s first notch, and the 3 dB
frequency, as outlined in Table 20. The on-chip digital filter provides a sinc3 (or (sinx/x)3) filter response. In association with the
gain selection, it also determines the output noise of the device. Changing the filter notch frequency, as well as the selected gain,
impacts resolution. Table 5 through Table 8 show the effects of filter notch frequency and gain on the output noise and effective
resolution of the part. The output data rate, or effective conversion time, for the device is equal to the frequency selected for
the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz, a new word is available at a 50 Hz output
rate, or every 20 ms. If the first notch is at 500 Hz, a new word is available every 2 ms. A calibration should be initiated when
any of these bits are changed. The settling time of the filter to a full-scale step input is worst case 4 × 1/(output data rate). For
example, with the filter-first notch at 50 Hz, the settling time of the filter to a full-scale step input is 80 ms maximum. If the first
notch is at 500 Hz, the settling time is 8 ms maximum. This settling time can be reduced to 3 × 1/(output data rate) by
synchronizing the step input change with a reset of the digital filter. In other words, if the step input takes place with the
FSYNC bit high, the settling time is 3 × 1/(output data rate) from the time when the FSYNC bit returns low. The 3 dB
frequency is determined by the programmed first notch frequency according to the relationship:
frequency
notch
first
filter
frequency
filter
-
262
.
0
dB
3
×
=
Table 20. Output Update Rates
FS1
FS0
Output Update Rate
3 dB Filter Cutoff
0
20 Hz
5.24 Hz
0
1
25 Hz
6.55 Hz
0
1
0
100 Hz
26.2 Hz
0
1
200 Hz
52.4 Hz
1
0
50 Hz
13.1 Hz
1
0
1
60 Hz
15.7 Hz
1
0
250 Hz
65.5 Hz
1
500 Hz
131 Hz
1 Assumes correct clock frequency on MCLK IN pin with the CLKDIV bit set appropriately.
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相关代理商/技术参数 |
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| AD7706BRUZ | 功能描述:IC ADC 16BIT 3CH 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7706BRUZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs |
| AD7706BRUZ-REEL | 功能描述:IC ADC 16BIT 3CHAN 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7706BRUZ-REEL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs |
| AD7706BRUZ-REEL7 | 功能描述:IC ADC 16BIT 3CHAN 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
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