参数资料
型号: AD7711AR-REEL7
厂商: Analog Devices Inc
文件页数: 4/28页
文件大小: 0K
描述: IC ADC 24BIT RTD I SOURCE 24SOIC
标准包装: 400
位数: 24
采样率(每秒): 1.03k
数据接口: 串行
转换器数目: 1
功率耗散(最大): 52.5mW
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 80°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极;1 个单端,双极;1 个差分,单极;1 个差分,双极
REV. G
–12–
AD7711
Figure 2 shows similar information to that outlined in Table I.
In these plots, however, the output rms noise is shown for the
full range of available cutoffs frequencies. The numbers given in
these plots are typical values at 25
∞C.
CIRCUIT DESCRIPTION
The AD7711 is a sigma-delta A/D converter with on-chip digital
filtering for measuring wide dynamic range, low frequency signals
such as those in RTD applications, industrial control, or process
control applications. It contains a sigma-delta (or charge-bal-
ancing) ADC, a calibration microcontroller with on-chip static
RAM, a clock oscillator, a digital filter, and a bidirectional serial
communications port.
The part contains two analog input channels, a programmable
gain differential analog input, and a programmable gain single-
ended input. The gain range is from 1 to 128 allowing the part
to accept unipolar signals of 0 mV to 20 mV and 0 V to 2.5 V
or bipolar signals in the range
±20 mV to ±2.5 V when the
reference input voltage equals 2.5 V. The input signal to the
selected analog input channel is continuously sampled at a
rate determined by the frequency of the master clock, MCLK
IN, and the selected gain (see Table III). A charge-balancing
A/D converter (sigma-delta modulator) converts the sampled
signal into a digital pulse train whose duty cycle contains the
digital information. The programmable gain function on the
analog input is also incorporated in this sigma-delta modulator
with the input sampling frequency being modified to give the
higher gains. A sinc3 digital low-pass filter processes the out-
put of the sigma-delta modulator and updates the output
register at a rate determined by the first notch frequency of
this filter. The output data can be read from the serial port
randomly or periodically at any rate up to the output register
update rate. The first notch of this digital filter (and therefore
its –3 dB frequency) can be programmed via an on-chip con-
trol register. The programmable range for this first notch
frequency is 9.76 Hz to 1.028 kHz, giving a programmable range
for the –3 dB frequency of 2.58 Hz to 269 Hz.
The basic connection diagram for the part is shown in Figure 3.
This figure shows the AD7711 in the external clocking mode
with both the AVDD and DVDD pins of the AD7711 being driven
from the analog 5 V supply. Some applications have separate
supplies for both AVDD and DVDD, and in some cases, the ana-
log supply exceeds the 5 V digital supply (see the Power Sup-
plies and Grounding section).
ANALOG
+5V SUPPLY
10 F
0.1 F
AVDD DVDD
AIN1(+)
AIN1(–)
AIN2
RTD1
AGND
VSS
DGND
REF OUT
REF IN(+)
VBIAS
REF IN(–)
RTD2
DRDY
TFS
RFS
SDATA
SCLK
A0
MODE
SYNC
MCLK OUT
MCLK IN
AD7711
DIFFERENTIAL
ANALOG INPUT
SINGLE-ENDED
ANALOG INPUT
ANALOG GROUND
DIGITAL GROUND
DATA READY
TRANSMIT (WRITE)
RECEIVE (READ)
SERIAL DATA
SERIAL CLOCK
ADDRESS INPUT
+5V
Figure 3. Basic Connection Diagram
The AD7711 provides a number of calibration options that can
be programmed via the on-chip control register. A calibration
cycle may be initiated at any time by writing to this control
register. The part can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. Other system components may also be included in
the calibration loop to remove offset and gain errors in the input
channel using the system calibration mode. Another option is a
background calibration mode where the part continuously
performs self-calibration and updates the calibration coeffi-
cients. Once the part is in this mode, the user does not have to
issue periodic calibration commands to the device or recalibrate
when there is a change in the ambient temperature or power
supply voltage.
The AD7711 gives the user access to the on-chip calibration
registers, allowing the microprocessor to read the device calibra-
tion coefficients and also to write its own calibration coefficients
to the part from prestored values in E
2PROM. This gives the
NOTCH FREQUENCY – Hz
10000
1000
0.1
10
10000
100
OUTPUT
NOISE
V
1000
100
10
1
GAIN OF 1
GAIN OF 2
GAIN OF 4
GAIN OF 8
Figure 2a. Output Noise vs. Gain and Notch
Frequency (Gains of 1 to 8)
NOTCH FREQUENCY – Hz
1000
0.1
10
10000
100
OUTPUT
NOISE
V
1000
100
10
1
GAIN OF 16
GAIN OF 32
GAIN OF 128
GAIN OF 64
Figure 2b. Output Noise vs. Gain and Notch
Frequency (Gains of 16 to 128)
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