参数资料
| 型号： | AD7713AN |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24-DIP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 15 |
| 位数： | 24 |
| 采样率（每秒）： | 205 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 5.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 24-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 24-PDIP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极；1 个差分，单极；1 个差分，双极 |
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REV. D
–8–
AD7713
Pin No. Mnemonic Function
16
RTD2
Constant Current Output. A nominal 200
A constant current is provided at this pin, which can be used as
the excitation current for RTDs. This current can be turned on or off via the control register. This second
current can be used to eliminate lead resistanced errors in 3-wire RTD configurations.
17
AIN3
Analog Input Channel 3. High level analog input that accepts an analog input voltage range of 4
VREF/GAIN.
At the nominal VREF of 2.5 V and a gain of 1, the AIN3 input voltage range is 0 V to
±10 V.
18
AGND
Ground Reference Point for Analog Circuitry.
19
TFS
Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data
expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after
TFS
goes low. In the external clocking mode,
TFS must go low before the first bit of the data-word is written to the part.
20
RFS
Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self-
clocking mode, both the SCLK and SDATA lines become active after
RFS goes low. In the external clocking
mode, the SDATA line becomes active after
RFS goes low.
21
DRDY
Logic Output. A falling edge indicates that a new output word is available for transmission. The
DRDY pin
will return high upon completion of transmission of a full output word.
DRDY is also used to indicate when
the AD7713 has completed its on-chip calibration sequence.
22
SDATA
Serial Data. Input/output with serial data being written to either the control register or the calibration regis-
ters and serial data being accessed from the control register, calibration registers, or the data register. During
an output data read operation, serial data becomes active after
RFS goes low (provided DRDY is low). Dur-
ing a write operation, valid serial data is expected on the rising edges of SCLK when
TFS is low. The output
data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.
23
DVDD
Digital Supply Voltage, 5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation.
24
DGND
Ground Reference Point for Digital Circuitry.
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con-
fused with bipolar zero), a point 0.5 LSB below the first code
transition (000...000 to 000...001) and full scale, a point 0.5 LSB
above the last code transition (111...110 to 111...111). The error
is expressed as a percentage of full scale.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transition
(111...110 to 111...111) from the ideal input full-scale voltage.
For AIN1(+) and AIN2(+), the ideal full-scale input voltage is
(AIN1(–) + VREF/GAIN – 3/2 LSBs), where AIN(–) is either
AIN1(–) or AIN2(–) as appropriate; for AIN3, the ideal full-scale
voltage is 4
VREF/GAIN – 3/2 LSBs. Positive full-scale error
applies to both unipolar and bipolar analog input ranges.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+) and AIN2(+), the ideal
input voltage is (AIN1(–) + 0.5 LSB); for AIN3, the ideal input
is 0.5 LSB when operating in the unipolar mode.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 ... 111 to
1000 ... 000) from the ideal input voltage. For AIN1(+) and
AIN2(+), the ideal input voltage is (AIN1(–) – 0.5 LSB); AIN3
can accommodate only unipolar input ranges.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
input voltage. For AIN1(+) and AIN2(+), the ideal input volt-
age is (AIN1(–) – VREF/GAIN + 0.5 LSB); AIN3 can only
accommodate unipolar input ranges.
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN1(+) and AIN2(+) inputs
greater than (AIN1(–) + VREF/GAIN) or on AIN3 of greater
than 4
VREF/GAIN (for example, noise peaks or excess voltages
due to system gain errors in system calibration routines) without
introducing errors due to overloading the analog modulator or
to overflowing the digital filter.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages on
AIN1(+) and AIN2(+) below (AIN1(–) – VREF/GAIN) without
overloading the analog modulator or overflowing the digital filter.
Offset Calibration Range
In the system calibration modes, the AD7713 calibrates its offset
with respect to the analog input. The offset calibration range
specification defines the range of voltages that the AD7713 can
accept and still calibrate offset accurately.
Full-Scale Calibration Range
This is the range of voltages that the AD7713 can accept in the
system calibration mode and still calibrate full scale correctly.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7713’s analog input define the analog input range. The
input span specification defines the minimum and maximum
input voltages from zero to full scale that the AD7713 can accept
and still calibrate gain accurately.
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