参数资料
| 型号： | AD7729ARZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/16页 |
| 文件大小： | 0K |
| 描述： | IC ADC 15BIT DUAL W/DAC 28SOIC |
| 标准包装： | 1,000 |
| 类型： | ADC，DAC |
| 分辨率（位）： | 15 b |
| 采样率（每秒）： | 270.8k |
| 数据接口： | 串行 |
| 电压电源： | 模拟和数字 |
| 电源电压： | 2.7 V ~ 3.3 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 带卷 (TR) |
AD7729
–7–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
Number
Mnemonic
Function
15
MCLK
Master Clock Input. MCLK is driven from a 13 MHz crystal. The active levels for MCLK are
determined by the value of DVDD2.
13
RESETB
Active Low Reset Signal. This input resets the entire AD7729 chip, resetting the control
registers and clearing the digital filters. The logic input levels (VINH and VINL) for RESETB
are determined by the value of DVDD2.
Power Supply
6
AVDD1
Analog Power Supply Connection for the Rx Section and the Bandgap Reference.
5
AVDD2
Analog Power Supply Connection for the Auxiliary Section.
7
AGND
Analog Ground Connection.
25
DVDD1
Digital Power Supply Connection.
24
DVDD2
Digital Power Supply Connection for the Serial Interface Section. This power supply also sets
the threshold voltages for RxON, RESETB and MCLK.
23
DGND
Digital Ground Connection.
Analog Signal and Reference
1, 2
IRxP, IRxN
Differential Analog Input for I Receive Channel.
3, 4
QRxP, QRxN
Differential Analog Input for Q Receive Channel.
26
AUXDAC
Analog Output Voltage from the 10-Bit Auxiliary DAC AUXDAC. This DAC is used for
functions such as Automatic Gain Control (AGC). The DAC possesses a register that is
accessible via the ASPORT or BSPORT. The DAC may be individually powered down.
28
REFCAP
A bypass capacitor to AGND of 0.1
F is required for the on-chip reference. The capacitor
should be fixed to this pin.
27
REFOUT
Buffered Reference Output, which has a nominal value of 1.3 V. A bypass capacitor (to
AGND) of 0.1
F is required on this pin.
Auxiliary Serial Port (ASPORT)
10
ASCLK
Serial Clock used to clock data or control bits to and from the auxiliary serial port (ASPORT).
The frequency of ASCLK is programmable and is equal to the frequency of the master clock
(MCLK) divided by an integer number.
9
ASDI
Serial Data Input of ASPORT. Both data and control information are input on this pin.
8
ASDIFS
Input Framing Signal for ASDI Serial Transfers.
20
ASDO
Serial Data Output of ASPORT. Both data and control information are output on this pin.
ASDO is in three-state when no information is being transmitted, thereby allowing external
control.
21
ASDOFS
Output Framing Signal for ASDO Serial Transfers.
22
ASE
ASPORT Enable. When ASE is low, the ASPORT is put into three-state thereby allowing
external control of the serial bus.
Baseband Serial Port (BSPORT)
16
BSCLK
Output serial clock used to clock data or control bits to and from the baseband serial port
(BSPORT). The frequency of BSCLK is programmable and is equal to the frequency of the
master clock (MCLK) divided by an integer number.
12
BSDI
Serial Data Input of BSPORT. Both data and control information are input on this pin.
11
BSDIFS
Input Framing Signal for BSDI Serial Transfers.
17
BSDO
Serial Data Output of BSPORT. Both data and control information are output on this pin.
BSDO is in three-state when no information is being transmitted, thereby allowing external
control.
18
BSDOFS
Output Framing Signal for BSDO Serial Transfers.
19
BSE
BSPORT Enable. When BSE is low, the BSPORT is put into three-state thereby allowing
external control of the serial bus.
ADCs
14
RxON
Receive Section Power-On Digital Input. The receive section is powered up by taking pin
RxON high. The receive section can alternatively be powered up by programming bit RxON
in baseband control register BCRA. When the powering up/down of the receive section is
being controlled by pin RxON, bit RxON should equal zero. Similarly, when the powering up/
down of the receive section is being controlled by bit RxON, pin RxON should be tied low.
The logic input levels (VINH and VINL) for RxON are determined by the value of DVDD2.
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| AD7730BNZ | 功能描述:IC ADC TRANSDUCER BRIDGE 24-DIP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
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