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| 型号： | AD7730BRZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/53页 |
| 文件大小： | 0K |
| 描述： | IC ADC BRDGE TRANSDCR 24SOIC TR |
| 标准包装： | 1,000 |
| 位数： | 24 |
| 通道数： | 1 |
| 功率（瓦特）： | 125mW |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 2.7 V ~ 5.25 V |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-AD7730LEBZ-ND - BOARD EVALUATION FOR AD7730 EVAL-AD7730EBZ-ND - BOARD EVAL FOR AD7730 |
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AD7730/AD7730L
–18–
Bit
Location
Mnemonic
Description
MR2
BO
Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout currents
connect to the selected analog input pair, one source current to the AIN(+) input and one sink current to
the AIN(–) input. A 0 in this bit turns off the on-chip burnout currents.
MR1–MR0
CH1–CH0
Channel Selection Bits. These bits select the analog input channel to be converted or calibrated as
outlined in Table XIII. With CH1 at 1 and CH0 at 0, the part looks at the AIN1(–) input internally
shorted to itself. This can be used as a test method to evaluate the noise performance of the part with
no external noise sources. In this mode, the AIN1(–) input should be connected to an external voltage
within the allowable common-mode range of the part. The Offset and Gain Calibration Registers on
the part are paired. There are three pairs of calibration registers labelled Register Pair 0 through Regis-
ter Pair 2. These are assigned to the input channel pairs as outlined in Table XIII.
Table XIII. Channel Selection
Input Channel Pair
CH1
CH0
Positive Input
Negative Input
Calibration Register Pair
0
AIN1(+)
AIN1(–)
Register Pair 0
0
1
AIN2(+)
AIN2(–)
Register Pair 1
1
0
AIN1(–)
Register Pair 0
1
AIN1(–)
AIN2(–)
Register Pair 2
Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 200010 Hex
The Filter Register is a 24-bit register from which data can be read or to which data can be written. This register determines the
amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode and the delay
associated with chopping the inputs. Table XIV outlines the bit designations for the Filter Register. FR0 through FR23 indicate the
bit location, FR denoting the bits are in the Filter Register. FR23 denotes the first bit of the data stream. The number in brackets
indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and
Figure 6 shows a flowchart for writing to the registers on the part.
Table XIV. Filter Register
FR23
FR22
FR21
FR20
FR19
FR18
FR17
FR16
SF11 (0)
SF10 (0)
SF9 (1)
SF8 (0)
SF7 (0)
SF6 (0)
SF5 (0)
SF4 (0)
FR15
FR14
FR13
FR12
FR11
FR10
FR9
FR8
SF3 (0)
SF2 (0)
SF1 (0)
SF0 (0)
ZERO (0)
SKIP (0)
FAST (0)
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
ZERO (0)
AC (0)
CHP (1)
DL3 (0)
DL2 (0)
DL1 (0)
DL0 (0)
Bit
Location
Mnemonic
Description
FR23–FR12
SF11–SF0
Sinc3 Filter Selection Bits. The AD7730 contains two filters: a sinc3 filter and an FIR filter. The 12 bits
programmed to SF11 through SF0 set the amount of averaging the sinc3 filter performs. As a result,
the number programmed to these 12 bits affects the –3 dB frequency and output update rate from the
part (see Filter Architecture section). The allowable range for SF words depends on whether the part
is operated with CHOP on or off and SKIP on or off. Table XV outlines the SF ranges for different
setups. All output update rates will be one-half those quoted in Table XV for the AD7730L operating
with a 2.4576 MHz clock.
REV. B
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