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参数资料
| 型号： | AD7780BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 1CH LP SD 16TSSOP |
| 设计资源： | Weigh Scale Design Using AD7780 with Internal PGA (CN0107) |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 16.7 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
AD7780
Rev. A | Page 12 of 16
The AD7780 has two gain options: gain = 1 and gain = 128.
When the GAIN pin is low, the gain is set to 128; when the
GAIN pin is high, the gain is set to 1. The acceptable analog
input range is ±VREF/gain. Thus, with VREF = 5 V, the input range
is ±5 V when the GAIN pin is high and ±39 mV when the GAIN
pin is low.
When the polarity of the GAIN pin is changed, the AD7780 modu-
lator and filter are reset immediately. DOUT/RDY is set high, and
the ADC then begins conversions. DOUT/RDY remains high until
the appropriate settling time for the filter elapses (see
Therefore, the user should complete any read operations before
changing the gain. Otherwise, 1s are read back from the AD7780
because the DOUT/
RDY pin is set high following the gain change.
The total settling time of the selected filter is required to generate
the first conversion after the gain change; subsequent conversions
occur at the selected update rate.
POWER-DOWN/RESET (PDRST)
The PDRST pin functions as a power-down pin and a reset pin.
When PDRST is taken low, the AD7780 is powered down. The
entire ADC is powered down (including the on-chip clock), the
low-side power switch is opened, and the DOUT/RDY pin is
tristated. The circuitry and serial interface are also reset, which
resets the logic, the digital filter, and the analog modulator.
PDRST must be held low for 100 ns minimum to initiate the
reset function (see
) .
When PDRST is taken high, the AD7780 is taken out of power-
down mode. When the on-chip clock has powered up (1 ms,
typically), the modulator begins sampling the analog input. The
low-side power switch is closed, and the DOUT/RDY pin
becomes active.
A reset is automatically performed on power-up.
ANALOG INPUT CHANNEL
The AD7780 has one differential analog input channel. The
input channel feeds into a high impedance input stage of the
amplifier. Therefore, the input can tolerate significant source
impedances and is tailored for direct connection to external
resistive-type sensors such as strain gages.
The absolute input voltage range is restricted to a range between
GND + 300 mV and AVDD 1.1 V. Care must be taken in setting
up the common-mode voltage to avoid exceeding these limits.
Otherwise, there is degradation in linearity and noise performance.
The low noise in-amp means that signals of small amplitude can
be amplified within the AD7780, while maintaining excellent noise
performance. The amplifier can be configured to have a gain of 128
or 1, using the GAIN pin. The analog input range is equal to
±VREF/gain. The common-mode voltage (AIN(+) + AIN())/2
must be ≥0.5 V.
BIPOLAR CONFIGURATION
The AD7780 accepts a bipolar input range. A bipolar input range
does not imply that the part can tolerate negative voltages with
respect to system GND. Signals on the AIN(+) input are refer-
enced to the voltage on the AIN() input. For example, if AIN()
is 2.5 V, the analog input range on the AIN(+) input is 2.46 V to
2.54 V for a gain of 128.
DATA OUTPUT CODING
The AD7780 uses offset binary coding. Thus, a negative full-
scale voltage results in a code of 000...000, a zero differential
input voltage results in a code of 100...000, and a positive full-
scale input voltage results in a code of 111...111.
The output code for any analog input voltage can be represented as
Code = 2N 1 × [(AIN × Gain /VREF) + 1]
where:
AIN is the analog input voltage.
Gain is 1 or 128.
N = 24.
REFERENCE
The AD7780 has a fully differential input capability for the channel.
The common-mode range for these differential inputs is GND to
AVDD. The reference input is unbuffered; therefore, excessive R-C
source impedances introduce gain errors. The reference voltage of
REFIN (REFIN(+) REFIN()) is AVDD nominal, but the AD7780
is functional with reference voltages of 0.5 V to AVDD. In applica-
tions where the excitation (voltage or current) for the transducer
on the analog input also drives the reference voltage for the part,
the effect of the low frequency noise in the excitation source is
removed because the application is ratiometric. If the AD7780
is used in a nonratiometric application, a low noise reference
should be used.
Recommended 2.5 V reference voltage sources for the AD7780
power references. These references have low output impedances
and are, therefore, tolerant to decoupling capacitors on REFIN(+)
without introducing gain errors in the system. Deriving the
reference input voltage across an external resistor means that
the reference input sees a significant external source impedance.
External decoupling on the REFIN pins is not recommended in
this type of circuit configuration.
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