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参数资料
| 型号： | AD7780BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 1CH LP SD 16TSSOP |
| 设计资源： | Weigh Scale Design Using AD7780 with Internal PGA (CN0107) |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 16.7 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
AD7780
Rev. A | Page 13 of 16
DOUT/RDY is reset high when the conversion has been read.
If the conversion is not read, DOUT/RDY goes high prior to the
data register update to indicate when not to read from the device.
This ensures that a read operation is not attempted while the reg-
ister is being updated. Each conversion can be read only once. The
data register is updated for every conversion. When a conversion
is complete, the serial interface is reset, and the new conversion is
placed in the data register. Therefore, the user must ensure that
the complete word is read before the next conversion is complete.
BRIDGE POWER-DOWN SWITCH
The bridge power-down switch (BPDSW) is useful in battery-
powered applications where the optimization of system power
consumption is essential. A 350 Ω load cell typically consumes
15 mA when excited with a 5 V power supply. To minimize the
current consumption, the load cell is disconnected when it is
not being used. The bridge power-down switch can be included
in series with the load cell. When PDRST is high, the bridge power-
down switch is closed, and the load cell measures the strain. When
PDRST is low, the bridge power-down switch is opened so no
current flows through the load cell. Therefore, the current
consumption of the system is minimized. The bridge power-
down switch has an on resistance of 9 Ω maximum. The switch
is capable of withstanding 30 mA of continuous current.
When PDRST is low, the DOUT/RDY pin is tristated. When
PDRST is taken high, the internal clock requires approximately
1 ms to power up. Following power-up, the ADC continuously
converts. The first conversion requires the total settling time (see
). DOUT/
RDY goes high when PDRST is taken high and
returns low only when a conversion is available. The ADC then
converts continuously, and subsequent conversions are avail-able
at the selected update rate.
shows the timing for a read
operation from the AD7780.
DIGITAL INTERFACE
The serial interface of the AD7780 consists of two signals: SCLK
and DOUT/RDY. SCLK is the serial clock input for the device,
and data transfers occur with respect to the SCLK signal. The
DOUT/RDY pin is dual purpose: it functions as a data ready pin
and as a data output pin. DOUT/RDY goes low when a new
data-word is available in the output register. A 32-bit word is
placed on the DOUT/RDY pin when sufficient SCLK pulses are
applied. This word consists of a 24-bit conversion result and eight
status bits.
shows the status bits, and
describes
the status bits and their functions.
When the filter response is changed (using FILTER) or the gain
is changed (using GAIN), the modulator and filter are reset
immediately (see Figure 5). DOUT/RDY is set high. The ADC
then begins conversions using the selected filter response/gain
setting. DOUT/RDY remains high until the appropriate settling
time for that filter has elapsed. Therefore, the user should complete
any read operations before changing the gain or update rate.
Otherwise, 1s are read back from the AD7780 because the
DOUT/RDY pin is set high following the gain/filter change.
07
94
5-
12
1
FILTER
ERR
RDY
ID1
ID0
GAIN
PAT1
PAT0
Figure 22. Status Bits
Table 9. Status Bit Functions
Bit Name
Description
RDY
Ready bit.
0: a conversion is available.
FILTER
Filter bit.
1: 10 Hz filter is selected
0: 16.7 Hz filter is selected.
ERR
Error bit.
1: an error occurred during conversion. (An error occurs when the analog input is outside the range.)
ID1, ID0
ID bits.
ID1
ID0
Function
0
1
Indicates the ID number for the AD7780
GAIN
Gain bit.
1: gain = 1.
0: gain = 128.
PAT1, PAT0
Status pattern bits. When the user reads data from the AD7780, a pattern check can be performed.
PAT1
PAT0
Function
0
1
Indicates that the serial transfer from the ADC was performed correctly (default).
0
Indicates that the serial transfer from the ADC was not performed correctly.
1
0
Indicates that the serial transfer from the ADC was not performed correctly.
1
Indicates that the serial transfer from the ADC was not performed correctly.
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