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| 型号： | AD7782BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 2CHAN 16TSSOP |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 19.79 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 3.9mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，单极；2 个差分，双极 |
AD7782
–8–
NOISE PERFORMANCE
Table I shows the output rms noise and output peak-to-peak
resolution in bits (rounded to the nearest 0.5 LSB) for the two
input voltage ranges. The numbers are typical and generated at
a differential input voltage of 0 V. The peak-to-peak resolution
figures represent the resolution for which there will be no code
flicker within a six-sigma limit. The output noise comes from
two sources. The first is the electrical noise in the semiconduc-
tor devices (device noise) used in the implementation of the
modulator. Secondly, when the analog input is converted into
the digital domain, quantization noise is added. The device
noise is at a low level and is independent of frequency. The
quantization noise starts at an even lower level but rises rapidly
with increasing frequency to become the dominant noise source.
Table I. Typical Output RMS Noise and
Peak-to-Peak Resolution vs. Input Range
Input Range
160 mV
2.56 V
Noise (
V)
0.65
2.30
Peak-to-Peak Resolution (Bits)
16.5
18.5
DIGITAL INTERFACE
The AD7782’s serial interface consists of four signals,
CS, SCLK,
DOUT/
RDY, and MODE. The MODE pin is used to select the
master/slave mode of operation. When the part is configured as
a master, SCLK is an output while SCLK is an input when
slave mode is selected. Data transfers take place with respect to
this SCLK signal. The DOUT/
RDY line is used for accessing
data from the data register. This pin also functions as a
RDY
line. When a conversion is complete, DOUT/
RDY goes low to
indicate that data is ready to be read from the AD7782’s data
register. It is reset high when a read operation from the data
register is complete. It also goes high prior to the updating of
the output register to indicate when not to read from the device
to ensure that a data read is not attempted while the register is
being updated. The digital conversion is also output on this pin.
CS is used to select the device and to place the device in standby
mode. When
CS is taken low, the AD7782 is powered up, the
PLL locks and the device initiates a conversion on the selected
channel. The device will continue to convert until
CS is taken
high. When
CS is taken high, the AD7782 is placed in standby
mode minimizing the current consumption. The conversion is
aborted, DOUT and SCLK are three-stated and the result in
the data register is lost.
Figure 2 shows the timing diagram for interfacing to the AD7782
with
CS used to decode the part.
MASTER MODE (MODE = 0)
In this mode, SCLK is provided by the AD7782. With
CS low,
SCLK becomes active when a conversion is complete and generates
twenty four falling and rising edges. The DOUT/
RDY pin, which
is normally high, goes low to indicate that a conversion is complete.
Data is output on the DOUT/
RDY pin following the SCLK falling
edge and is valid on the SCLK rising edge. When the 24-bit word
has been output, SCLK idles high until the next conversion is
complete. DOUT/
RDY returns high and will remain high until
another conversion is available. It then operates as a
RDY signal
again. The part will continue to convert until
CS is taken high.
SCLK and DOUT/
RDY are three-stated when CS is taken high.
SLAVE MODE (MODE = 1)
In slave mode, the SCLK is generated externally. SCLK must
idle high between data transfers. With
CS low, DOUT/RDY
goes low when a conversion is complete. Twenty four SCLK
pulses are needed to transfer the digital word from the AD7782.
Twenty four consecutive pulses can be generated or, alterna-
tively, the data transfer can be split into batches. This is useful
when interfacing to a microcontroller which uses 8-bit transfers.
Data is output following the SCLK falling edge and is valid on
the SCLK rising edge.
CIRCUIT DESCRIPTION
Analog Input Channels
The ADC has two fully differential input channels. Pin
CH1/CH2
is used to select the channels. When
CH1/CH2 is low, channel
AIN1(+) – AIN1(–) are selected while channel AIN2(+) – AIN2(–)
are selected when
CH1/CH2 is high. When the analog input
channel is switched, the settling time of the part must elapse
before a new valid word is available from the ADC.
The output of the ADC multiplexer feeds into a high-impedance
input stage of the buffer amplifier. As a result, the ADC inputs
can handle significant source impedances and are tailored for direct
connection to external resistive-type sensors like strain gages or
Resistance Temperature Detectors (RTDs).
The absolute input voltage range on the ADC inputs is restricted
to a range between GND + 100 mV and VDD – 100 mV. Care
must be taken in setting up the common-mode voltage and input
voltage range so that these limits are not exceeded; otherwise
there will be a degradation in linearity and noise performance.
Programmable Gain Amplifier
The output from the buffer on the ADC is applied to the input of
the on-chip programmable gain amplifier (PGA). The PGA gain
range is programmed via pin RANGE. With an external 2.5 V refer-
ence applied, the PGA can be programmed to have a bipolar range
of
±160 mV (RANGE = 0) or ±2.56 V (RANGE = 1). These
are the ranges that should appear at the input to the on-chip PGA.
REV. A
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