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参数资料
| 型号： | AD7787BRMZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 2CH LP SIG 10MSOP |
| 标准包装： | 3,000 |
| 位数： | 24 |
| 采样率（每秒）： | 120 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 225µW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极；1 个单端，双极；1 个差分，单极；1 个差分，双极 |
Data Sheet
AD7787
Rev. A | Page 11 of 20
Table 6. Register Selection
RS1
RS0
Register
Register Size
0
Communications Register during a Write Operation
8-Bit
0
Status Register during a Read Operation
8-Bit
0
1
Mode Register
8-Bit
1
0
Filter Register
8-Bit
1
Data Register
24-Bit
Table 7. Channel Selection
CH1
CH0
Channel
0
AIN1(+) AIN1()
0
1
AIN2
1
0
AIN1() AIN1()
1
VDD Monitor
STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0×8C)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bits RS1 and RS0 with 0s. Table 8 outlines the bit designations for the status register. SR0
through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in the parenthesis indicates the power-on/reset default status of that bit.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY (1)
ERR (0)
0 (0)
1 (1)
CH1 (0)
CH0 (0)
Table 8. Status Register Bit Designations
Bit
Location
Bit
Name
Description
SR7
RDY
Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the
ADC data register has been read or a period of time before the data register is updated with a new conversion result
to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode.
The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status
register for monitoring the ADC for conversion data.
SR6
ERR
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC
data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange. Cleared by a write
operation to start a conversion.
SR5 to
SR4
0
These bits are automatically cleared.
SR3 to
SR2
1
These bits are automatically set.
SR1 to
SR0
CH1 to
CH0
These bits indicate which channel is being converted by the ADC.
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