参数资料
型号: AD7787BRMZ-RL
厂商: Analog Devices Inc
文件页数: 5/20页
文件大小: 0K
描述: IC ADC 24BIT 2CH LP SIG 10MSOP
标准包装: 3,000
位数: 24
采样率(每秒): 120
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 225µW
电压电源: 单电源
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极;1 个单端,双极;1 个差分,单极;1 个差分,双极
Data Sheet
AD7787
Rev. A | Page 13 of 20
FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0×04)
The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output
word rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are
in the filter register. FR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status
of that bit.
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
0 (0)
CDIV1 (0)
CDIV0 (0)
0 (0)
FS2 (1)
FS1 (0)
FS0 (0)
Table 11. Filter Register Bit Designations
Bit
Location
Bit Name
Description
FR7 to
FR6
0
These bits must be programmed with a Logic 0 for correct operation.
FR5 to
FR4
CLKDIV1
to CDIV0
These bits are used to operate the AD7787 in the lower power modes. The clock is internally divided and the
power is reduced. In the low power modes, the update rates will scale with the clock frequency so that dividing
the clock by 2 causes the update rate to be reduced by a factor of 2 also.
00
Normal Mode
01
Clock Divided by 2
10
Clock Divided by 4
11
Clock Divided by 8
FR3
0
This bit must be programmed with a Logic 0 for correct operation.
FR2 to
FR0
FS2 to FS0
These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and the
noise. Table 12 shows the allowable update rates when normal power mode is used. In the low power modes, the
update rate is scaled with the clock frequency. For example, if the internal clock is divided by a factor of 2, the
corresponding update rates are divided by 2 also.
Table 12. Update Rates
FS2
FS1
FS0
fADC (Hz)
f3dB (Hz)
RMS Noise (V)
Rejection
0
120
28
40
25 dB @ 60 Hz
0
1
100
24
25
25 dB @ 50 Hz
0
1
0
33.3
8
3.36
0
1
20
4.7
1.6
80 dB @ 60 Hz
1
0
16.6
4
1.5
65 dB @ 50 Hz/60 Hz (Default Setting)
1
0
1
16.7
4
1.5
80 dB @ 50 Hz
1
0
13.3
3.2
1.2
1
9.5
2.3
1.1
67 dB @ 50 Hz/60 Hz
DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0×000000)
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the RDY bit/pin is set.
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