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参数资料
| 型号： | AD7797BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIG-DEL 1CH 16TSSOP |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 123 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1.6mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
| 配用： | EVAL-AD7797EBZ-ND - BOARD EVALUATION FOR AD7797 |
AD7796/AD7797
Rev. A | Page 12 of 24
STATUS REGISTER
RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communication register,
select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 11 outlines the bit designations for the status
register. SR0 through SR7 indicate the bit locations, with SR denoting that the bits are in the status register. SR7 denotes the first bit of the
data stream. The number in brackets indicates the power-on/reset default status of that bit.
MSB
LSB
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY(1)
ERR(0)
0(0)
CH2(0)
CH1(0)
CH0(0)
Table 11. Status Register Bit Designations
Bit Location
Bit Name
Description
SR7
RDY
Ready Bit for ADC. Cleared when data is written to the ADC data register. Set automatically after the ADC data
register has been read or before the data register is updated with a new conversion result to indicate to the
user not to read the conversion data. It is also set when the part is placed in power-down mode. DOUT/RDY
also indicates the end of a conversion and can be used as an alternative to the status register for monitoring
the ADC for conversion data.
SR6
ERR
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the
ADC data register has been clamped to all 0s or all 1s. Error sources include overrange and underrange.
Cleared by a write operation to start a conversion.
SR5 to SR3
0
These bits are automatically cleared.
SR2 to SR0
CH2 to CH0
These bits indicate the channel that is being converted by the ADC.
MODE REGISTER
RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A
The mode register is a 16-bit read/write register. This register is used to select the operating mode, update rate, and clock source. Table 12
outlines the bit designations for this register. MR0 through MR15 indicate the bit locations, with MR denoting that the bits are in the
mode register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that
bit. Any write to the setup register resets the modulator and filter, and sets the RDY bit.
MSB
LSB
MR15
MR14
MR13
MR12
MR11
MR10
MR9
MR8
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
MD2(0)
MD1(0)
MD0(0)
0(0)
CLK1(0)
CLK0(0)
0(0)
FS3(1)
FS2(0)
FS1(1)
FS0(0)
Table 12. Mode Register Bit Designations
Bit Location
Bit Name
Description
MR15 to MR13
MD2 to MD0
Mode Select Bits. These bits select the operational mode of the AD7796/AD7797 (see Table 13).
MR12 to MR8
0
These bits must be programmed with a Logic 0 for correct operation.
MR7 to MR6
CLK1 to CLK0
These bits are used to select the clock source for the AD7796/AD7797. Either an on-chip 64 kHz clock
or an external clock can be used. The ability to override using an external clock allows several AD7796/
AD7797 devices to be synchronized. In addition, 50 Hz/60 Hz rejection is improved when an accurate
external clock drives the AD7796/AD7797.
CLK1
CLK0
ADC Clock Source
0
Internal 64 kHz Clock. Internal clock is not available at the CLK pin.
0
1
Internal 64 kHz Clock. This clock is made available at the CLK pin.
1
0
External 64 kHz Clock Used. An external clock gives better 50 Hz/60 Hz rejection.
See Table 1 for the external clock specifications.
1
External Clock Used. The external clock is divided by 2 within the AD7796/AD7797.
MR5 to MR4
0
These bits must be programmed with a Logic 0 for correct operation.
MR3 to MR0
FS3 to FS0
Filter Update Rate Select Bits (see Table 14).
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