参数资料
| 型号： | AD7801BRU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/16页 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT PARALLEL INP 20TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 75 |
| 设置时间： | 1.2µs |
| 位数： | 8 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 12.9mW |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
| 输出数目和类型： | 1 电压，单极；1 电压，双极 |
| 采样率（每秒）： | 833k |
AD7801
–9–
REV. 0
VOUT = 2 ×V REF
N
256
where:
N
is the decimal equivalent of the binary input
code. N ranges from 0 to 255.
VREF is the voltage applied to the external REFIN pin
when the external reference is selected and is VDD/2
if the internal reference is used.
Table I. Output Voltage for Selected Input Codes
Digital
Analog Output
MSB . . . LSB
1111 1111
2
×
255
256
×V
REF V
1111 1110
2
×
254
256
×V
REF V
1000 0001
2
×
129
256
×V
REF V
1000 0000
V
REF V
0111 1111
2
×
127
256
×V
REF V
0000 0001
2
×
V REF
256
V
0000 0000
0 V
2VREF
VREF
0
DAC
OUTPUT
VOLTAGE
DAC INPUT CODE
00 01
7F 80 81
FE FF
Figure 26. DAC Transfer Function
POWER-ON RESET
The AD7801 has a power-on reset circuit designed to allow
output stability during power up. This circuit holds the DAC in
a reset state until a write takes place to the DAC. In the reset
state all zeros are latched into the input register of the DAC and
the DAC register is in transparent mode thus the output of the
DAC is held at ground potential until a write takes place to the
DAC. The power-on reset circuitry generates a PON STRB
signal which is a gating signal used within the logic to identify
a power-on condition.
POWER-DOWN FEATURES
The AD7801 has a power-down feature implemented by
exercising the external
PD pin. An active low signal puts the
complete DAC into power-down mode. When in power-down,
the current consumption of the device is reduced to less than
1
A max at +25°C or 2 A max over temperature, making the
device suitable for use in portable battery powered equipment.
The internal reference resistors, the reference bias servo loop,
the output amplifier and associated linear circuitry are all shut
down when the power-down is activated. The output terminal
sees a load of
≈ 23 k to GND when in power-down mode as
shown in Figure 25. The contents of the data register are
unaffected when in power-down mode. The device typically
comes out of power-down in 13
s (see Figure 10).
VDD
11.7k
11.7k
IDAC
VREF
Figure 25. Output Stage During Power-Down
Analog Outputs
The AD7801 contains a voltage output DAC with 8-bit resolution
and rail-to-rail operation. The output buffer provides a gain of
two at the output. Figures 2, 3 and 4 show the source and sink
capabilities of the output amplifier. The slew rate of the output
amplifier is typically 7.5 V/
s and has a full-scale settling to
eight bits with a 100 pF capacitive load in typically 1.2
s.
The input coding to the DAC is straight binary. Table I shows
the binary transfer function for the AD7801. Figure 26 shows
the DAC transfer function for binary coding. Any DAC output
voltage can be expressed as:
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