参数资料
型号: AD7829BRW-1RL7
厂商: Analog Devices Inc
文件页数: 9/20页
文件大小: 0K
描述: IC ADC 8BIT 8CH 2MSPS 28-SOIC
标准包装: 400
位数: 8
采样率(每秒): 2M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 36mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 带卷 (TR)
输入数目和类型: 8 个单端,单极
AD7829-1
Rev. 0 | Page 17 of 20
EOC
PARALLEL INTERFACE
The parallel interface of the AD7829-1 is eight bits wide. Figure 23
shows a timing diagram illustrating the operational sequence of
the AD7829-1 parallel interface. The multiplexer address is latched
into the AD7829-1 on the falling edge of the RD input. The on-
chip track/hold goes into hold mode on the falling edge of
CONVST. A conversion is also initiated at this point. When the
conversion is complete, the end of conversion line (EOC) pulses
low to indicate that new data is available in the output register
of the AD7829-1. The EOC pulse stays logic low for a maximum
time of 110 ns.
However, the
pulse can be reset high by a rising edge of
RD
EOC
. This
line can be used to drive an edge-triggered
interrupt of a microprocessor. CS
RD
and
going low accesses
the 8-bit conversion result. It is possible to tie CS permanently
low and use only RD to access the data. In systems where the
part is interfaced to a gate array or ASIC, this EOC pulse can be
applied to the CS
RD
and
inputs to latch data out of the
AD7829-1 and into the gate array or ASIC. This means that the
gate array or ASIC does not need any conversion status
recognition logic, and it also eliminates the logic required in the
gate array or ASIC to generate the read signal for the AD7829-1.
CONVST
EOC
CS
RD
DB0 TO DB7
A0 TO A2
t1
t4
t5
t6
t7
t8
t3
t9
t10
t11
t12
t13
VALID
DATA
NEXT
CHANNEL
ADDRESS
t2
06
17
9-
0
24
Figure 23. AD7829-1 Parallel Port Timing
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