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参数资料
| 型号： | AD7945TQ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | +3.3 V/+5 V Multiplying 12-Bit DACs |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.7 us SETTLING TIME, 12-BIT DAC, CDIP20 |
| 封装： | GLASS SEALED, CERDIP-20 |
| 文件页数： | 12/16页 |
| 文件大小： | 329K |
| 代理商： | AD7945TQ |
AD7943/AD7945/AD7948
REV. B
–5–
(TA = TMIN to TMAX, unless otherwise noted)
Limit @
Parameter
VDD = +3 V to +3.6 V
VDD = +4.5 V to +5.5 V
Units
Description
tSTB
2
60
40
ns min
STB Pulsewidth
tDS
15
10
ns min
Data Setup Time
tDH
35
25
ns min
Data Hold Time
tSRI
55
35
ns min
SRI Data Pulsewidth
tLD
55
35
ns min
Load Pulsewidth
tCLR
55
35
ns min
CLR Pulsewidth
tASB
0
ns min
Min Time Between Strobing Input Shift
Register and Loading DAC Register
tSV
3
60
35
ns max
STB Clocking Edge to SRO Data Valid Delay
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1
s on any digital input.
2STB mark/space ratio range is 60/40 to 40/60.
3t
SV is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Specifications subject to change without notice.
tSTB
STB1,
STB2,
STB4
STB3
tDS
tDH
tSRI
SRI
DB11(N)
(MSB)
DB10(N)
DB0(N)
DB0(N–1)
DB10(N–1)
LD1,
LD2,
CLR
SRO
tSV
tLD, tCLR
tASB
Figure 1. AD7943 Timing Diagram
TO OUTPUT
PIN
CL
50pF
1.6mA
IOL
+2.1V
IOH
200 A
Figure 2. Load Circuit for Digital Output Timing Specifications
AD7943 TIMING SPECIFICATIONS1
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