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参数资料
| 型号： | AD7945TQ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | +3.3 V/+5 V Multiplying 12-Bit DACs |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.7 us SETTLING TIME, 12-BIT DAC, CDIP20 |
| 封装： | GLASS SEALED, CERDIP-20 |
| 文件页数： | 13/16页 |
| 文件大小： | 329K |
| 代理商： | AD7945TQ |
AD7943/AD7945/AD7948
REV. B
–6–
AD7945 TIMING SPECIFICATIONS1 (T
A = TMIN to TMAX, unless otherwise noted)
Limit @
Parameter
VDD = +3 V to +3.6 V
VDD = +4.5 V to +5.5 V
Units
Description
tDS
35
20
ns min
Data Setup Time
tDH
10
ns min
Data Hold Time
tCS
60
40
ns min
Chip Select Setup Time
tCH
0
ns min
Chip Select Hold Time
tWR
60
40
ns min
Write Pulsewidth
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
DATA VALID
CS
tCH
tDS
tDH
WR
DB11–DB0
tCS
tWR
Figure 3. AD7945 Timing Diagram
AD7948 TIMING SPECIFICATIONS1 (T
A = TMIN to TMAX, unless otherwise noted)
Limit @
Parameter
VDD = +3 V to +3.6 V
VDD = +4.5 V to +5.5 V
Units
Description
tDS
45
30
ns min
Data Setup Time
tDH
10
ns min
Data Hold Time
tCWS
0
ns min
CSMSB or CSLSB to WR Setup Time
tCWH
0
ns min
CSMSB or CSLSB to WR Hold Time
tLWS
0
ns min
LDAC to WR Setup Time
tLWH
0
ns min
LDAC to WR Hold Time
tWR
60
40
ns min
Write Pulsewidth
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
DATA
VALID
DATA
VALID
WR
tCWS
tCWH
tCWS
tCWH
tLWH
tLWS
tDH
tDS
tWR
tDH
tDS
CSMSB
CSLSB
LDAC
DB7–DB0
Figure 4. AD7948 Timing Diagram
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