参数资料
型号: AD7946BRMZ
厂商: Analog Devices Inc
文件页数: 8/24页
文件大小: 0K
描述: IC ADC 14BIT 500KSPS SAR 10-MSOP
标准包装: 50
系列: PulSAR®
位数: 14
采样率(每秒): 500k
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 19mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
输入数目和类型: 1 个伪差分,单极
产品目录页面: 780 (CN2011-ZH PDF)
配用: EVAL-AD7946CBZ-ND - BOARD EVALUATION FOR AD7946
AD7946
Rev. A | Page 16 of 24
AD7946
REF
GND
VDD
IN–
IN+
VIO
SDI
SCK
SDO
CNV
100nF
10F
ADR364
33
2.7nF
0V TO 4.096V
ADA4841
100nF
>5.2V
100nF
04
65
6
-05
2
Figure 32. Example of a Single-Supply Application Circuit
DIGITAL INTERFACE
Although the AD7946 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7946, when in CS mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, for example, Blackfin ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals mini-
mizes wiring connections useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
The AD7946, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The operating mode depends on the SDI level when the CNV
rising edge occurs. CS mode is selected if SDI is high, and chain
mode is selected if SDI is low. The SDI hold time is such that
when SDI and CNV are connected, the chain mode is always
selected.
In either mode, the AD7946 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
BUSY indicator feature is enabled
In CS mode, if CNV or SDI is low when the ADC
conversion ends (see Figure 36 and Figure 40).
In chain mode, if SCK is high during the CNV rising edge
(see Figure 44).
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