参数资料
型号: AD7983BCPZ-RL7
厂商: Analog Devices Inc
文件页数: 7/24页
文件大小: 0K
描述: IC ADC 16BIT 1.33MSPS 10LFCSP
标准包装: 1
系列: PulSAR®
位数: 16
采样率(每秒): 1.33M
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 12mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘,CSP
供应商设备封装: 10-LFCSP-WD(3x3)
包装: 标准包装
输入数目和类型: 1 个差分,单极
其它名称: AD7983BCPZ-RL7DKR
AD7983
Rev. A | Page 15 of 24
VOLTAGE REFERENCE INPUT
The AD7983 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for example,
a reference buffer using the AD8031 or the AD8605, a ceramic
chip capacitor is appropriate for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, a reference-decoupling capacitor value as small as
2.2 μF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
POWER SUPPLY
The AD7983 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and 5.0 V. To reduce the
number of supplies needed, VIO and VDD can be tied together.
The AD7983 is independent of power supply sequencing between
VIO and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 25.
80
55
1
1000
FREQUENCY (kHz)
P
S
RR
(
d
B)
10
100
75
70
65
60
06
97
4-
01
0
Figure 25. PSRR vs. Frequency
To ensure optimum performance, VDD should be roughly half
of REF, the voltage reference input. For example, if REF is 5.0 V,
VDD should be set to 2.5 V (±5%).
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