参数资料
型号: AD7984BCPZ-RL
厂商: Analog Devices Inc
文件页数: 14/24页
文件大小: 0K
描述: IC ADC 18BIT 1.33MSPS 10LFCSP
设计资源: Converting a Single-Ended Signal with AD7984 Differential PulSAR ADC (CN0033)
标准包装: 5,000
系列: PulSAR®
位数: 18
采样率(每秒): 1.33M
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 14mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘,CSP
供应商设备封装: 10-LFCSP-WD(3x3)
包装: 带卷 (TR)
输入数目和类型: 1 个差分,单极
AD7984
Rev. A | Page 21 of 24
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7984s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7984s is shown in
Figure 36, and the corresponding timing is given in Figure 37.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7984 enters the acquisition phase and
goes into standby mode. The remaining data bits stored in the
internal shift register are clocked by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first, and 18 × N clocks are
required to read back the N ADCs. The data is valid on both
SCK edges. Although the rising edge can be used to capture the
data, a digital host using the SCK falling edge will allow a faster
reading rate and consequently more AD7984s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time.
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7984
SDI
SDO
CNV
B
SCK
AD7984
SDI
SDO
CNV
A
SCK
06
97
3-
0
26
Figure 36. Chain Mode Without Busy Indicator Connection Diagram
SDOA = SDIB
DA17
DA16
DA15
SCK
12
3
34
35
36
tSSDISCK
tHSDISCK
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
16
17
tSCK
tSCKL
tSCKH
DA0
19
20
18
SDIA = 0
SDOB
DB17
DB16
DB15
DA1
DB1DB0DA17
DA16
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
06
97
3-
02
7
Figure 37. Chain Mode Without Busy Indicator Serial Interface Timing
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