参数资料
型号: AD8141ACPZ-RL
厂商: Analog Devices Inc
文件页数: 9/24页
文件大小: 0K
描述: IC VIDEO AMP TRPL DIFF 24LFCSP
标准包装: 5,000
应用: 驱动器
输出类型: 差分
电路数: 3
-3db带宽: 275MHz
转换速率: 1150 V/µs
电流 - 电源: 44mA
电压 - 电源,单路/双路(±): 4.5 V ~ 5.5 V,±2.25 V ~ 2.75 V
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘,CSP
供应商设备封装: 24-LFCSP-WQ(4x4)
包装: 带卷 (TR)
Data Sheet
AD8141/AD8142
Rev. A | Page 17 of 24
The desired differential output in this example is 1.4 V p-p
because the terminated input signal is 0.7 V p-p and the closed-
loop gain = 2. The actual differential output voltage is equal to
(0.725 V p-p)(2 k/1038.3 ) = 1.4 V p-p. This illustrates how
the two aforementioned effects cancel for large RF and RG.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the output impedance of
the drivers to reduce phase margin, resulting in high frequency
ringing in the pulse response. The best way to minimize this effect
is to place the source termination resistors immediately at the
amplifier outputs to minimize parasitic capacitances formed by
unnecessarily long traces.
DISABLE
The AD8141 and AD8142 have disable pins that, when pulled high,
significantly reduce the power consumed while simultaneously
placing the outputs in high-Z states. The disable feature can be
used to multiplex two drivers. See Figure 17, Figure 19, and
Figure 22 for the disabled input-to-output isolation, output
impedance, and response performance. The threshold levels
for the disable pin are listed in Table 1.
An output glitch occurs whenever the disable feature is asserted or
deasserted. See the Applications Information section for details.
AD8142 SYNC-ON-COMMON-MODE
The AD8142 includes on-chip, sync-on-common-mode circuitry
that encodes externally applied HSYNC and VSYNC signals onto the
common-mode output voltages of each of the R, G, and B drivers.
The circuit encodes the horizontal and vertical sync pulses in a
way that results in low radiated energy. A simplified circuit that
illustrates how the pulses are encoded is shown in Figure 41.
For a more detailed description of the sync scheme, see the
The sync-on-common-mode circuit generates a current based
on the voltage applied to the SYNC LEVEL input pin (Pin 18)
with respect to the negative supply. With SYNC LEVEL input
tied to VS, the common-mode output of all drivers is set at 1.5 V
above the negative supply. Using a resistor divider, a voltage can
be applied between VS and SYNC LEVEL that determines the
maximum deviation of the common-mode outputs from their
midsupply level. If, for instance, SYNC LEVEL VS = 0.5 V
and the supply voltage is 5 V, then the common-mode outputs
fall within an envelope of 1.5 V ± 0.5 V. The state of each VOUT,cm
output based on the HSYNC and VSYNC inputs is determined by
the equations defined in the Applications Information section.
For the positive supplies between 2.5 V and 5 V, the sync-on-
common-mode circuit can be used by directly applying standard
HSYNC and VSYNC signals to the respective AD8142 inputs. These
inputs adhere to standard logic thresholds (see Table 1 for the
exact levels). The HSYNC and VSYNC inputs, therefore, can be
driven directly off the output of a computer video card without
concern of being overdriven. The input path from the HSYNC and
VSYNC inputs to the switches in the current mode level-shifting
circuit are well matched to eliminate false switching transients. This
maximizes common-mode balance and minimizes radiated energy.
H
V
H
R
H
V
VS–
BLUE VOCM
SYNC LEVEL
HSYNC
VSYNC
VS+
H
V
H
R
V
MIRROR
V
RED VOCM
GREEN VOCM
09461-
039
Figure 41. Sync-On-Common-Mode Simplified Circuit
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