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参数资料
| 型号： | IDT70V38L20PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 1.125MBIT 20NS 100TQFP |
| 标准包装： | 6 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 1.125M（64K x 18） |
| 速度： | 20ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 70V38L20PF |
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/ S = V IH ) (2,4,5)
t WC
ADDR "A"
MATCH
t WP
R/ W "A"
DATA IN "A"
t DW
VALID
t DH
ADDR "B"
t APS
(1)
MATCH
BUSY "B"
DATA OUT "B"
NOTES:
t BAA
t WDD
t DDD (3)
t BDA
t BDD
VALID
4850drw 11
1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S = V IL (SLAVE).
2. CE L = CE R = V IL, refer to Chip Enable Truth Table.
3. OE = V IL for the reading port.
4. If M/ S = V IL (slave), BUSY is an input. Then for this example BUSY "A" = V IH and BUSY "B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/ S = V IL )
t WP
R/ W "A"
t WB (3)
BUSY "B"
R/ W "B"
(2)
t WH (1)
NOTES:
1. t WH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/ W "B" , until BUSY "B" goes HIGH.
3. t WB is only for the 'slave' version.
11
4850 drw 12
.
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