参数资料
型号: IDT70V38L20PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 6/17页
文件大小: 0K
描述: IC SRAM 1.125MBIT 20NS 100TQFP
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 1.125M(64K x 18)
速度: 20ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 70V38L20PF
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3.3V
3.3V
Input Rise/Fall Times
3ns Max.
590 ?
590 ?
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1 and 2
DATA OUT
BUSY
INT
435 ?
30pF
DATA OUT
435 ?
5pF*
4850 tbl 11
4850 drw 03
Figure 1. AC Output Load
4850 drw 04
Figure 2. Output Test Load
(for t LZ , t HZ , t WZ , t OW )
* Including scope and jig.
Waveform of Read Cycles (5)
t RC
ADDR
CE
t ACE
(6)
t AA
(4)
(4)
t AOE
(4)
OE
t ABE (4)
UB , LB
R/ W
DATA OUT
t LZ
(1)
VALID DATA
(4)
t OH
BUSY OUT
t HZ
(2)
Timing of Power-Up Power-Down
CE (6)
t PU
I CC
t BDD
(3,4)
t PD
4850 drw 05
I SB
50%
50%
4850 drw 06
.
NOTES:
1. Timing depends on which signal is asserted last, OE , CE , LB or UB .
2. Timing depends on which signal is de-asserted first CE , OE , LB or UB .
3. t BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t AOE , t ACE , t AA or t BDD .
5. SEM = V IH .
6. Refer to Truth Table I - Chip Enable.
6
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