参数资料
型号: AD823AARZ-RL
厂商: Analog Devices Inc
文件页数: 11/20页
文件大小: 0K
描述: IC OPAMP FET RR 17MHZ DUAL 8SOIC
标准包装: 2,500
放大器类型: J-FET
电路数: 2
输出类型: 满摆幅
转换速率: 35 V/µs
-3db带宽: 19MHz
电流 - 输入偏压: 1.3pA
电压 - 输入偏移: 700µV
电流 - 电源: 6.3mA
电流 - 输出 / 通道: 44mA
电压 - 电源,单路/双路(±): 3 V ~ 36 V,±1.5 V ~ 18 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 带卷 (TR)
Data Sheet
AD823A
Rev. | Page 19 of 20
MAXIMIZING PERFORMANCE THROUGH PROPER
LAYOUT
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD823A, care
should be taken in the circuit board layout. The PCB surface
must remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
reduces surface moisture and provides a humidity barrier, reducing
parasitic resistance on the board. The use of guard rings around the
amplifier inputs further reduces leakage currents. Figure 48 shows
how the guard rings should be configured, and Figure 49 shows
the top view of how a surface-mount layout can be arranged. The
guard ring does not need to be a specific width, but it should form
a continuous loop around both inputs. By setting the guard ring
voltage equal to the voltage at the non-inverting input, parasitic
capacitance is minimized as well. For further reduction of leakage
currents, components can be mounted to the PCB using Teflon
standoff insulators.
VOUT
VIN
AD823A
VIN
AD823A
VIN
AD823A
09439-
152
Figure 48. Guard Ring Layout and Connections to
Reduce PCB Leakage Currents
V–
V+
VREF
VIN1
VIN2
GUARD
RING
R1
R2
R1
AD823A
GUARD
RING
09439-
153
Figure 49. Top View of AD823A SOIC Layout with Guard Rings
B
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