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参数资料
| 型号： | AD8313-EVAL |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 0.1 GHz-2.5 GHz, 70 dB Logarithmic Detector/Controller |
| 中文描述： | 0.1千兆赫，2.5千兆赫，70分贝的对数检测器/控制器 |
| 文件页数： | 9/16页 |
| 文件大小： | 261K |
| 代理商： | AD8313-EVAL |
AD8313
–9–
REV. B
With Pins 7 and 8 disconnected (controller mode), the output
may be stated as
V
OUT
v
V
S
when
V
SLOPE
(P
IN
+
100
) > V
SET
V
OUT
v
0
when
V
SLOPE
(P
IN
+
100
) < V
SET
when the input is stated in terms of the power of a sinusoidal
signal across a net termination impedance of 50
. The transi-
tion zone between high and low states is very narrow, since the
output stage behaves essentially as a fast integrator. The above
equations may be restated as
V
OUT
v
V
S
when
V
SLOPE
log (
V
IN
/2.2
μ
V
) >
V
SET
V
OUT
v
0
when
V
SLOPE
log (
V
IN
/2.2
μ
V
) <
V
SET
A further use of the separate VOUT and VSET pins is in raising
the load-driving current capability by the inclusion of an ex-
ternal NPN emitter follower. More complete information about
usage in these various modes is provided in the Applications
section.
INTERFACES
This section describes the signal and control interfaces and their
behavior. On-chip resistances and capacitances exhibit varia-
tions of up to
±
20%. These resistances are sometimes tempera-
ture dependent and the capacitances may be voltage dependent.
Power-Down Interface, PWDN
The power-down threshold is accurately centered at the midpoint
of the supply as shown in Figure 22. If Pin 5 is left unconnected or
tied to the supply voltage (recommended) the bias enable cur-
rent is shut off, and the current drawn from the supply is pre-
dominately through a nominal 300 k
chain (20
μ
A at 3 V). When
grounded, the bias system is turned on. The threshold level is
accurately at V
POS
/2. The input bias current at the
PWDN pin
when operating in the device “ON” state is approximately
5
μ
A for V
POS
= 3 V.
5
PWDN
VPOS
75k
V
6
COMM
150k
V
50k
V
150k
V
TO BIAS
ENABLE
4
Figure 22. Power-Down Threshold Circuitry
Signal Inputs, INHI, INLO
The simplest low frequency ac model for this interface consists
of just a 900
resistance R
IN
in shunt with a 1.1 pF input ca-
pacitance, C
IN
connected across INHI and
INLO. Figure 23
shows these distributed in the context of a more complete sche-
matic. The input bias voltage shown is for the enabled chip;
when disabled, it will rise by a few hundred millivolts. If the
input is coupled via capacitors, this change may cause a low-
level signal transient to be introduced, having a time-constant
formed by these capacitors and R
IN
. For this reason, large-
valued coupling capacitors should be well matched; this is not
necessary when using the small capacitors found in many im-
pedance transforming networks used at high frequencies.
1.25k
V
COMM
VPOS
INHI
INLO
VPOS
0.5pF
0.5pF
0.7pF
2.5k
V
2.5k
V
~
0.75V
(1ST DETECTOR)
250
V
~
1.4mA
125
V
125
V
1.25k
V
1.24V
GAIN BIAS
TO 2ND
STAGE
TO STAGES
1 THRU 4
1
2
3
4
Figure 23. Input Interface Simplified Schematic
For high frequency use, Figure 24 shows the input impedance
plotted on a Smith chart. This measured result of a typical de-
vice includes a 191 mil 50
trace and a 680 pF capacitor to
ground from the INLO pin.
1.1pF
900
V
1.9GHz
Fr100MHz
1.9GHz
2.5GHz
R
55
22
23
+j X
–j 43
AD8313 MEASURED
2.5GHz
900MHz
100MHz
Figure 24. Typical Input Impedance
Logarithmic/Error Output, VOUT
The rail-to-rail output interface is shown in Figure 25. V
OUT
can run from within about 50 mV of ground, to within about
100 mV of the supply voltage, and is short-circuit safe to either
supply. However, the sourcing load current I
SOURCE
is limited by
that provided by the PNP transistor, to typically 400
μ
A. Larger
load currents can be provided by adding an external NPN tran-
sistor (see Applications). The dc open-loop gain of this amplifier
is high, and it may be regarded essentially as an integrator hav-
ing a capacitance of 2 pF (C
INT
) driven by the current-mode
signals generated by the summed outputs of the nine detector
stages, which is scaled approximately 4.0
μ
A/dB.
COMM
g
m
STAGE
C
INT
LP
LM
10mA
MAX
VOUT
C
L
BIAS
I
SOURCE
400
m
A
VPOS
FROM
SET-POINT
SUMMED
DETECTOR
OUTPUTS
6
8
1
Figure 25. Output Interface Circuitry
Thus, for a midscale RF input of about 3 mV, which is some
40 dB above the minimum detector output, this current is
160
μ
A and the output changes by 8 V/
μ
s. When VOUT is
connected to VSET, the rise and fall times are approximately
40 ns (for R
L
≥
10 k
). The nominal slew rate is
±
2.5 V/
μ
s.
The HF compensation technique results in stable operation with
a large capacitive load, C
L
, though the positive-going slew rate
will then be limited by I
SOURCE
/C
L
to 1 V/
μ
s for C
L
= 400 pF.
相关PDF资料 |
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|---|---|
| AD8313 | 0.1 GHz－2.5 GHz,70dB Logarithmic Detector/Controller(频率为0.1 GHz－2.5 GHz,增益为70dB的对数检测器/控制器) |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD8313-EVALZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| AD8314 | 制造商:AD 制造商全称:Analog Devices 功能描述:100 MHz to 2.7 GHz, 45 dB RF Detector/Controller |
| AD8314_06 | 制造商:AD 制造商全称:Analog Devices 功能描述:100 MHz to 2.7 GHz, 45 dB RF Detector/Controller |
| AD8314ACP-EVAL | 制造商:Analog Devices 功能描述:EVAL BD 100 MHZ TO 2.7 GHZ, 45 DB RF DETECTOR/CNTRLR - Bulk |
| AD8314ACP-EVALZ | 制造商:Analog Devices 功能描述:AD8314 RF DETECTOR EVAL BOARD 制造商:Analog Devices 功能描述:AD8314, RF DETECTOR, EVAL BOARD 制造商:Analog Devices 功能描述:AD8314, RF DETECTOR, EVAL BOARD, Silicon Manufacturer:Analog Devices, Silicon Co 制造商:Analog Devices 功能描述:AD8314, RF DETECTOR, EVAL BOARD, Silicon Manufacturer:Analog Devices, Silicon Core Number:(Not Applicable), Kit Application Type:(Not Available), Application Sub Type:-, SVHC:No SVHC (20-Jun-2013) , RoHS Compliant: Yes |
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