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参数资料
| 型号： | AD8321AR-REEL |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通用总线功能 |
| 英文描述： | Gain Programmable CATV Line Driver |
| 中文描述： | LINE DRIVER, PDSO20 |
| 封装： | MS-013AC, SOIC-20 |
| 文件页数： | 8/19页 |
| 文件大小： | 660K |
| 代理商： | AD8321AR-REEL |
AD8321
–8–
REV. 0
The attenuation setting in the AD8321 is determined by the
8-bit word in the data latch. The SDATA load sequence is
initiated by a falling edge on
DATEN
. The gain control data
(SDATA) is serially loaded (MSB first) into the 7-bit shift register
at each rising edge of the clock. See Figure 24. While
DATEN
is low, the data latch holds the previous data word allowing the
attenuation level to remain unchanged. After eight clock cycles
the new data word is fully loaded and
DATEN
is switched high.
This enables the data latch and the loaded register data is passed to
the attenuator with the updated gain value. Also at this
DATEN
transition, the internal clock is disabled, thus inhibiting new
serial input data.
The power amplifier has two basic modes of operation. A for-
ward mode (or power-up mode) and a reverse mode (or power-
down) mode. In the power-up mode (
PD
= 1), the power
amplifier stage is enabled and the AD8321 has a maximum gain
of 20 V/V or 26 dB (into 75
). With a total attenuation of
53.43 dB in the DAC, vernier and preamp, the AD8321’s total
gain range is 26 dB to –27.43 dB. In both the forward or reverse
mode the single-ended output signal maintains a dc level of
V
CC
/2. This dc output level provides for optimum large signal
linearity.
In the power-down mode (
PD
= 0), the power amplifier is
turned off and a “reverse” amplifier (the inner triangle in Figure
22) is enabled. During this 1-to-0 transition, the output power
is disabled. This assures that S11 and S22 remain approximately
equal to zero thus minimizing line reflections. In the time do-
main, as
PD
switches states, a transitional glitch and pedestal
offset results (See Figures 14 and 15). These anomalies have
been minimized by temperature compensated internal circuitry
and laser trimming. The powered down supply current drops to
52 mA versus 90 mA in the power-up mode.
APPLICATIONS
General Application
The AD8321 is primarily intended for use as the return path
(also called upstream path) Power Amplifier (PA) or line driver
in cable modem applications. Upstream data is modulated in
either QPSK or QAM format. This is done either in DSP or by
a dedicated QPSK/QAM modulator such as the AD9853 or
other modem/modulator chip. The amplifier receives its input
signal either from the dedicated QPSK/QAM modulator or from
a DAC. In both cases, the signal must be low-pass filtered be-
fore being applied to the line driving amplifier. Because the
distance to the central office varies from cable modem sub-
scriber to subscriber, resulting in various line losses, signals from
various subscribers will require attenuation while others may
require gain. As a result, the AD8321 line driver is required to
vary its output applying attenuation or gain as needed so that all
signals arriving at the central office are of the same amplitude.
DOCSIS (Data Over Cable Service Interface Specifications)
requires a cable modem output signal ranging in power from a
minimum of 8 dBmV to a maximum of 58 dBmV. In cable
modem applications where DOCSIS compliance is desired, the
AD8321 amplifier must be used in conjunction with a 75
matching attenuator connected between the AD8321 output
and the low-pass input port of the diplexer. See the schematic in
Figure 28. The matching attenuator is used to achieve DOCSIS-
compliant noise levels at the lower end of the AD8321 output
power range. The insertion loss of a diplexer is typically less
than 1 dB. As a result of these combined losses, the PA line
driver must be capable of delivering sufficient power into a 75
load while maintaining reasonable distortion performance at the
output of the modem. (See sections containing “DOCSIS” for
further information. All references to DOCSIS pertain to
SP-RFI-I04-980724 entitled Radio Frequency Interface
Specification.)
T
ES
VALIMSB. . . .LSB
GAIN TRANSFER (G1)
T
DS
T
EH
8 CLOCK CYCLES
GAIN TRANSFER (G2)
T
OFF
T
GS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PD
PEDESTAL
CLK
SDATA
DATEN
T
ON
T
C
T
WH
VALID DATA WORD G2
Figure 24. Serial Interface Timing
相关PDF资料 |
PDF描述 |
|---|---|
| AD8321-EVAL | Gain Programmable CATV Line Driver |
| AD8321AR | Gain Programmable CATV Line Driver |
| AD8322ARU-REEL | 5 V CATV Line Driver Coarse Step Output Power Control |
| AD8322-EVAL | 5 V CATV Line Driver Coarse Step Output Power Control |
| AD8322ARU | 5 V CATV Line Driver Coarse Step Output Power Control |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD8321ARZ | 功能描述:IC LINE DRIVER CATV 3.3V 20SOIC RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| AD8321ARZ2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Gain Programmable CATV Line DRiver |
| AD8321ARZ-REEL | 功能描述:IC LINE DVR CATV 20-SOIC T/R RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| AD8321ARZ-REEL2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Gain Programmable CATV Line DRiver |
| AD8321-EVAL | 功能描述:BOARD EVAL FOR AD8321 RoHS:否 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 主要目的:电源管理，电池充电器 嵌入式:否 已用 IC / 零件:MAX8903A 主要属性:1 芯锂离子电池 次要属性:状态 LED 已供物品:板 |
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