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| 型号： | AD8328ARQ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | IC LINE DRIVE CABLE 5V 20-QSOP |
| 产品变化通告： | AD8328 Discontinuation 02/Mar/2012 |
| 标准包装： | 56 |
| 类型： | 线路驱动器，发射器 |
| 应用： | 调制解调器，机顶盒 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-QSOP |
| 包装： | 管件 |
AD8328
Rev. A | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD8328
TXEN
SDATA
VCC
CLK
VIN+
SLEEP
BYP
NC
VOUT+
NC = NO CONNECT
GND
VIN–
GND
RAMP
VOUT–
GND
VCC
DATEN
GND
03
15
8-
0
05
Figure 5. 20-Lead QSOP Pin Configuration
TOP VIEW
(Not to Scale)
AD8328
1
2
3
4
5
15
14
13
12
11
16
17
20 19 18
67
8
9 10
GND
VIN+
VIN–
GN
D
GN
D
V
CC
V
CC
TX
E
N
GN
D
SL
EEP
DA
T
E
N
S
DAT
A
CL
K
RAMP
VOUT+
VOUT–
BYP
NC
03
15
8-
00
6
Figure 6. 20-Lead LFCSP Pin Configuration
Table 5. 20-Lead QSOP and 20-Lead LFCSP Pin Function Descriptions
Pin No.
20-Lead
QSOP
Pin No.
20-Lead
LFCSP
Mnemonic
Description
1, 3, 4, 7,
11, 20
1, 2, 5, 9,
18, 19
GND
Common External Ground Reference.
2, 19
17, 20
VCC
Common Positive External Supply Voltage. A 0.1 μF capacitor must decouple each pin.
5
3
VIN+
Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor.
6
4
VIN
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor.
8
6
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register.
A Logic 0-to-Logic 1 transition transfers the latched data to the attenuator core (updates the gain)
and simultaneously inhibits serial data transfer into the register.
A Logic 1-to-Logic 0 transition inhibits the data latch (holds the previous gain state) and
simultaneously enables the register for serial data load.
9
7
SDATA
Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the
internal register with the most significant bit (MSB) first.
10
8
CLK
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit
master-slave register.
A Logic 0-to-Logic 1 transition latches the data bit, and a Logic 1-to-Logic 0 transfers the data bit
to the slave. This requires the input serial data-word to be valid at or before this clock transition.
12
10
SLEEP
Low Power Sleep Mode. In the sleep mode, the AD8328’s supply current is reduced to 20 μA.
A Logic 0 powers down the part (high ZOUT state), and a Logic 1 powers up the part.
13
11
NC
No Connect.
14
12
BYP
Internal Bypass. This pin must be externally ac-coupled (0.1 μF capacitor).
15
13
VOUT
Negative Output Signal
16
14
VOUT+
Positive Output Signal
17
15
RAMP
External RAMP Capacitor (Optional)
18
16
TXEN
Logic 0 Disables Forward Transmission. Logic 1 enables forward transmission.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD8328ARQ-EVAL | 制造商:AD 制造商全称:Analog Devices 功能描述:5 V Upstream Cable Line Driver |
| AD8328ARQ-REEL | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 5.25V 20-Pin QSOP T/R |
| AD8328ARQZ | 功能描述:IC LINE DRIVE CABLE 5V 20-QSOP RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| AD8328ARQZ-REEL | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 5.25V 20-Pin QSOP T/R 制造商:Rochester Electronics LLC 功能描述:QSOP LOW COST +5V CABLE LINE DRIVER - Tape and Reel 制造商:Analog Devices 功能描述:IC,Digitally Controlled Gain Amplifier,SINGLE,SSOP,20PIN,PLASTIC |
| AD8330 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Cost, DC to 150 MHz Variable Gain Amplifier |
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