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| 型号： | AD8330-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD8330 |
| 标准包装： | 1 |
| 每 IC 通道数： | 1 - 单 |
| 放大器类型： | 可变增益 |
| 输出类型： | 差分，满摆幅 |
| 转换速率： | 1500 V/µs |
| -3db带宽： | 150MHz |
| 工作温度： | -40°C ~ 85°C |
| 电流供应（主 IC）： | 20mA |
| 电压 - 电源，单路/双路(±)： | 2.7 V ~ 6 V |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD8330 |
| 产品目录页面： | 775 (CN2011-ZH PDF) |
| 相关产品： | AD8330ACPZ-R7DKR-ND - IC AMP VGA 150MHZ LN LP 16LFCSP AD8330ACPZ-R2-ND - IC AMP VGA 150MHZ LN LP 16LFCSP AD8330ACPZ-RL-ND - IC AMP VGA 150MHZ LN LP 16LFCSP AD8330ACPZ-R7CT-ND - IC AMP VGA 150MHZ LN LP 16LFCSP AD8330ACPZ-R7TR-ND - IC AMP VGA 150MHZ LN LP 16LFCSP AD8330ARQZ-RL-ND - IC AMP VGA 150MHZ LN LP 16QSOP AD8330ARQZ-R7-ND - IC AMP VGA 150MHZ LN LP 16QSOP AD8330ARQZ-ND - IC AMP VGA 150MHZ LN LP 16QSOP |
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AD8330
Data Sheet
Rev. F | Page 16 of 32
Alternatively, this can be expressed as a numerical gain
magnitude
V
BN
DBS
G
6
.
0
10
=
(2)
The gain can be increased or decreased by changing the voltage,
VMAG, applied to the VMAG pin. The internally set default value
of 500 mV is derived from the same band gap reference that
determines the decibel scaling. The tolerance on this voltage,
and mismatches in certain on-chip resistors, cause small gain
errors (see the Specifications section). Though not all appli-
cations of VGAs demand accurate gain calibration, it is a
valuable asset in many situations, for example, in reducing
design tolerances.
Figure 47 shows the core circuit in more detail. The range and
scaling of VDBS is independent of the supply voltage, and the
gain control pin, VDBS, presents a high incremental input re-
sistance (~100 MΩ) with a low bias current (~100 nA), making
the AD8330 easy to drive from a variety of gain control sources.
Inversion of the Gain Slope
The AD8330 supports many features that further extend the
versatility of this VGA in wide bandwidth gain control systems.
For example, the logic pin, MODE, allows the slope of the gain
function to be inverted, so that the basic gain starts at +50 dB
for a gain voltage, VDBS, of zero and runs down to 0 dB when
this voltage is at its maximum specified value of 1.5 V. The basic
forms of these two gain control modes are shown in Figure 48.
0.25
10
20
VDBS (V)
G
AI
N
(
d
B)
0
30
40
50
0
0.50
0.75
1.0
1.25
1.50
MODE PIN
LOW, GAIN
DECREASES
WITH VDBS
MODE PIN
HIGH, GAIN
INCREASES
WITH VDBS
03217-
049
Figure 48. Two Gain Directions of the AD8330
Gain Magnitude Control (VMAG)
In addition to the basic linear-in-dB control, two more gain
control features are provided. The voltage applied to Pin VMAG
provides accurate linear-in-magnitude gain control with a very
rapid response. The bandwidth of this interface is >100 MHz.
When this pin is unconnected, VMAG assumes its default value of
500 mV (see Figure 47) to set up the basic 0 dB to 50 dB range.
However, any voltage from ~15 mV to 5 V can be applied either
to lower the gain by up to 30 dB or to raise it by 20 dB. The
combined gain span is thus 100 dB, that is, the 50 dB basic gain
span provided by VDBS plus a 60 dB linear-in-magnitude span
provided by VMAG. The latter modifies the basic numerical gain
GBN to generate a total gain, expressed here in magnitude terms.
V
5
.
0
MAG
BN
T
V
G
G =
(3)
Using this to calculate the output voltage,
VOUT = 2 × GIN × VIN × VMAG
(4)
from which it is apparent that the AD8330 implements a linear,
two-quadrant multiplier with a bipolar VIN and a unipolar VMAG.
Because the AD8330 is a dc-coupled system, it can be used in
many applications where a wideband two-quadrant multiplier
function is required, from dc up to about 100 MHz from either
input (VIN or VMAG).
As VMAG is varied, so also is the peak output magnitude, up to a
point where this is limited by the absolute output limit imposed
by the supply voltage. In the absence of the latter effect, the
peak output into an open-circuited load is just
VOUT_PK = ±4 VMAG
(5)
whereas for a load resistance of RL directly across OPHI and
OPLO, it is
(
)
150
2
_
+
±
=
L
MAG
PK
OUT
R
V
(6)
RL = O/C, VDBS = 0 V, VIN is swept from 2.5 V dc to +2.5 V dc, and
VMAG is set to 0.25 V, 0.5 V, 1 V, and 2 V. Except for the last value
of VMAG, the peak output follows Equation 5. This exceeds the
supply-limited value when VMAG = 2 V and the peak output is
±5.65 V, that is, ±6 V 0.35 V. Figure 50 demonstrates the high
speed multiplication capability. The signal input is a 100 MHz,
0.1 V sine wave, VDBS is set to 0.6 V, and VMAG is a square wave at
5 MHz alternating from 0.25 V to 1 V. The output is ideally a
sine wave switching in amplitude between 0.5 V and 2 V.
VIN ( V)
8
3
1
2
–
3
–
V
O
UT
(V)
4
0
–4
–8
–1
6
2
–2
–6
0
2
VMAG = 2V
1V
0.5V
0.25V
03217-
050
Figure 49. Effect of VMAG on Gain and Peak Output
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