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| 型号： | AD8339ACPZ-R7 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 调制器/解调器 |
| 英文描述： | 0 MHz - 50 MHz RF/MICROWAVE I/Q DEMODULATOR |
| 封装： | 6 X 6 MM, ROHS COMPLIANT, MO-220-VJJD-2, LFCSP-40 |
| 文件页数： | 16/36页 |
| 文件大小： | 2970K |
| 代理商： | AD8339ACPZ-R7 |
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AD8339
Rev. A | Page 23 of 36
SERIAL INTERFACE
The AD8339 contains a 4-wire, SPI-compatible digital interface
(SDI, SCLK, CSB, and SDO). The interface comprises a 20-bit
shift register plus a latch. The shift register is loaded MSB first.
Phase selection and channel enabling information are contained
in the 20-bit word. Figure 56 is a bit map of the data-word, and
Figure 57 is the timing diagram.
The shift direction is to the right with MSB first. Because the
latch is implemented with D-flip-flops (DFF) and CSB acts as
the clock to the latch, any time that CSB is low, the latch flip-
flops monitor the shift register outputs. As soon as CSB goes
high, the data present in the register is latched. New data can be
loaded into the shift register at any time.
Twenty bits are required to program each AD8339; the data is
transferred from the register to the latch when CSB goes high.
Depending on the data, the corresponding channels are enabled,
and the phases are selected. Figure 57 illustrates the timing for
two sequentially programmed devices.
Note that the data is latched into the register flip-flops on the
rising edge of SCLK. SDO also transitions on the rising edge
of SCLK.
ENBL BITS
When all four ENBL bits are low, only the SPI port is powered
up. This feature allows for low power consumption (~13 mW
per AD8339 or 3.25 mW per channel) when the CW Doppler
function is not needed. Because the SPI port stays alive even
with the rest of the chip powered down, the part can be awakened
again by simply programming the port. As soon as the CSB signal
goes high, the part turns on again. Note that this takes a fair
amount of time because of the external capacitor on the LODC
pin. It takes ~10 μs to 15 μs with the recommended 0.1 μF
decoupling capacitor. The decoupling capacitor on this pin is
intended to reduce bias noise contribution in the LO divider
chain. The user can experiment with the value of this decoupling
capacitor to determine the smallest value without degrading the
dynamic range within the frequency band of interest.
The SPI also has an additional pin that can be used in a test
mode or as a quick way to reset the SPI and depower the chip.
All bits in both the shift register and the latch are reset low
when the RSTS pin is pulled above ~1.5 V. For quick testing
without the need to program the SPI, the voltage on the RSTS
pin should be first pulled high and then pulled to 1.4 V. This
enables all four channels in the phase (I = 1, Q = 0) state (all
phase bits are 0000); the channel enable bits are all set to 1. This
is an untested threshold not intended for continuous operation.
06
58
7-
05
4
TO PHASE SELECT AND
BIAS BLOCKS FOR
CHANNEL ENABLES
TO CHANNEL 1 PHASE
SELECT BLOCK
TO CHANNEL 2 PHASE
SELECT BLOCK
TO CHANNEL 3 PHASE
SELECT BLOCK
TO CHANNEL 4 PHASE
SELECT BLOCK
SHIFT
REGISTER
LATCH
SCLK
SDI
CH 1
CH 3 CH 4
CH 3 CH 3
CH 4 CH 4
CH 4
CH 1 CH 1 CH 1 CH 1 CH 2 CH 2 CH 2 CH 2
CH 2
CH 1
CH 3 CH 4
CH 3 CH 3
CH 4 CH 4
CH 4
CH 1 CH 1 CH 1 CH 1 CH 2 CH 2 CH 2 CH 2
CH 2
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
SDO
TO NEXT
AD8339
ENABLE BITS
PH SEL CH 1
PH SEL CH 2
PH SEL CH 3
PH SEL CH 4
RSTS
CSB
TO OTHER
AD8339s
TO OTHER
AD8339s
Figure 56. Serial Interface Showing the 20-Bit Shift Register and Latch
06
58
7-
05
5
CSB
t1
t2
t7
t8
t3
t4
t5
t6
SCLK
SDI
SDO
DATA FOR AD8339 #1
DATA FOR AD8339 #2
Figure 57. Timing Diagram
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