参数资料
| 型号： | AD8366ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/28页 |
| 文件大小： | 0K |
| 描述： | IC DUAL AMP VGA 32LFCSP |
| 标准包装： | 1 |
| 放大器类型： | 可变增益 |
| 电路数： | 2 |
| 输出类型： | 差分 |
| 转换速率： | 1100 V/µs |
| -3db带宽： | 600MHz |
| 电流 - 电源： | 180mA |
| 电压 - 电源，单路/双路(±)： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ |
| 包装： | 标准包装 |
| 其它名称： | AD8366ACPZ-R7DKR |
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AD8366
Rev. A | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
24
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO GROUND.
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
VPSIA
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
VPSIB
BIT0/CS
BIT1/SDAT
BIT2/SCLK
BIT3
OCOM
BIT4
BIT5
DENA
DE
C
A
OFS
A
CC
M
A
VC
MA
VP
S
O
A
OP
P
A
OP
M
A
SE
N
B
DE
CB
OF
S
B
CC
M
B
VC
M
B
VP
S
O
B
O
PPB
OP
M
B
DE
NB
AD8366
TOP VIEW
(Not to Scale)
07
58
4-
0
28
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 8, 13, 28
VPSIA, VPSIB, VPSOB,
VPSOA
Input and Output Stage Positive Supply Voltage (4.75 V to 5.25 V).
2, 3, 6, 7
IPPA, IPMA, IPMB,
IPPB
Differential Inputs.
4
ENBL
Chip Enable. Pull this pin high to enable.
5, 20
ICOM, OCOM
Input and Output Ground Pins. Connect these pins via the lowest possible impedance to
ground.
9, 32
DECB, DECA
VPOS/2 Reference Decoupling Node. Connect a decoupling capacitor from these nodes to
ground.
10, 31
OFSB, OFSA
Output Offset Correction Loop Compensation. Connect a capacitor from these nodes to
ground to enable the correction loop. Tie this pin to ground to disable.
11, 30
CCMB, CCMA
Connect These Nodes to Ground.
12, 29
VCMB, VCMA
Output Common-Mode Setpoint. These pins default to VPOS/2 if left open. Drive these pins
from a low impedance source to change the output common-mode voltage.
14, 15, 26, 27
OPPB, OPMB, OPMA,
OPPA
Differential Outputs.
16, 17
DENB, DENA
Data Enable. Pull these pins high to address each or both channels for parallel gain
programming. These pins are not used in serial mode.
18, 19, 21, 22, 23, 24
BIT5, BIT4, BIT3,
BIT2/SCLK, BIT1/SDAT,
BIT0/CS
Parallel Data Path (When SENB Is Low). When SENB is high, BIT0 becomes a chip select (CS),
BIT1 becomes a serial data input (SDAT), and BIT2 becomes a serial clock (SCLK). BIT3 to BIT5
are not used in serial mode.
25
SENB
Serial Interface Enable. Pull this pin high for serial gain programming mode and pull this pin low
for parallel gain programming mode.
EPAD
The exposed pad must be connected to ground.
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