参数资料
型号: AD8370ARE-REEL7
厂商: Analog Devices Inc
文件页数: 9/28页
文件大小: 0K
描述: IC AMP VGA DIFF LN 16TSSOP
标准包装: 1,000
放大器类型: 可变增益
电路数: 1
输出类型: 差分
转换速率: 5750 V/ns
-3db带宽: 750MHz
电流 - 输入偏压: 400pA
电流 - 电源: 79mA
电压 - 电源,单路/双路(±): 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
供应商设备封装: 16-TSSOP-EP
包装: 带卷 (TR)
Data Sheet
AD8370
Rev. B | Page 17 of 28
The AD8370 contains both digital and analog sections. Care
should be taken to ensure that the digital and analog sections
are adequately isolated on the PC board. The use of separate
ground planes for each section connected at only one point via
a ferrite bead inductor ensures that the digital pulses do not
adversely affect the analog section of the AD8370.
Due to the nature of the AD8370’s circuit design, care must be
taken to minimize parasitic capacitance on the input and output.
The AD8370 could become unstable with more than a few pF of
shunt capacitance on each input. Using resistors in series with
input pins is recommended under conditions of high source
capacitance.
High transient and noise levels on the power supply, ground,
and digital inputs can, under some circumstances, reprogram the
AD8370 to an unintended gain code. This further reinforces the
need for proper supply bypassing and decoupling. The user
should also be aware that probing the AD8370 and associated
circuitry during circuit debug may also induce the same effect.
PACKAGE CONSIDERATIONS
The package of the AD8370 is a compact, thermally enhanced
TSSOP 16-lead design. A large exposed paddle on the bottom of
the device provides both a thermal benefit and a low inductance
path to ground for the circuit. To make proper use of this pack-
aging feature, the PCB needs to make contact directly under the
device, connected to an ac/dc common ground reference with
as many vias as possible to lower the inductance and thermal
impedance.
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
AD8370
INHI
ICOM
VCCI
PWUP
VOCM
VCCO
OCOM
OPHI
OPLO
OCOM
VCCO
LTCH
CLCK
DATA
ICOM
INLO
6
7
8
2
3
5
1
11
10
9
15
14
16
13
12
4
SERIAL CONTROL
INTERFACE
0.1
F
1nF
0.1
F
+VS
CAC
RL
SINGLE-
ENDED
SOURCE
RS
03692-045
Figure 47. Single-Ended-to-Differential Conversion
The AD8370 is primarily designed for differential signal inter-
facing. The device can be used for single-ended-to-differential
conversion simply by terminating the unused input to ground
using a capacitor as depicted in Figure 47. The ac coupling
capacitors should be selected such that their reactance is
negligible at the frequency of operation. For example, using
1 nF capacitors for CAC presents a capacitive reactance of
j1.6 on each input node at 100 MHz. This attenuates the
applied input voltage by 0.003 dB. If 10 pF capacitors had been
selected, the voltage delivered to the input would be reduced
by 2.1 dB when operating with a 200 source impedance.
DIFFERENTIAL
BALANCE
(dB)
–1.0
0
–0.5
0.5
0
100
200
300
400
500
FREQUENCY (MHz)
03692-046
HIGH GAIN MODE
(GAIN CODE HG255)
LOW GAIN MODE
(GAIN CODE LG127)
Figure 48. Differential Output Balance for a Single-Ended Input Drive at
Maximum Gain (RL = 1 k, CAC = 10 nF)
Figure 48 illustrates the differential balance at the output for a
single-ended input drive for multiple gain codes. The differential
balance is better than 0.5 dB for signal frequencies less than
250 MHz. Figure 49 depicts the differential balance over the
entire gain range at 10 MHz. The balance is degraded for lower
gain settings because the finite common gain allows some of the
input signal applied to INHI to pass directly through to the
OPLO pin. At higher gain settings, the differential gain dominates
and balance is restored.
0
0.1
0.2
0.3
0.4
0.5
0.6
DIFFERENTIAL
BALANCE
(dB)
0
96
32
64
0
32
64
96
128
GAIN CODE
03692-047
LOW GAIN MODE
HIGH GAIN MODE
Figure 49. Differential Output Balance at 10 MHz for a Single-Ended Drive vs.
Gain Code (RL = 1 k, CAC = 10 nF)
Even though the amplifier is no longer being driven in a balanced
manner, the distortion performance remains adequate for most
applications. Figure 50 illustrates the harmonic distortion
performance of the circuit in Figure 47 over the entire gain range.
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