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参数资料
| 型号： | AD8522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | +5 Volt, Serial Input,Dual 12-Bit DAC(串行输入,双12位D/A转换器) |
| 中文描述： | 5伏，串行输入，双12位DAC（串行输入，双12位的D / A转换器） |
| 文件页数： | 6/8页 |
| 文件大小： | 189K |
| 代理商： | AD8522 |
AD8522
input register and transferring the 12 bits of data into the de-
coded address determined by the address bits A and B in the se-
rial input register.
Unipolar Output Operation
T his is the basic mode of operation for the AD8522. T he
AD8522 has been designed to drive loads as low as 820
in
parallel with 500 pF. T he code table for this operation is shown
in T able III.
T able III. Unipolar Code T able
Hexadecimal
Number in
DAC Register
Decimal
Number in
DAC Register
Analog
Output
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
+4.095
+2.049
+2.048
+2.047
0
5
2
0
1
3
4
10
100
100k
10k
1k
R
TIED TO AGND
DATA = FFF
H
V
DD
= +5V
T
A
= +25
°
C
R
TIED TO +5V
DATA = 000
H
LOAD RESISTANCE –
O
V
IN
H = +5V
V
IN
L = 0V
Figure 6. Output Swing vs. Load
80
60
40
20
0
–20
–40
–60
–80
1
2
3
OUTPUT VOLTAGE – Volts
O
DATA = 800
H
POSITIVE
CURRENT
LIMIT
NEGATIVE
CURRENT
LIMIT
Figure 9. I
OUT
vs. V
OUT
5.2
5.0
4.8
4.6
4.4
4.2
4.0
0.01
0.1
100
10
1.0
OUTPUT LOAD CURRENT – mA
V
D
V
≤
1 LSB
DATA = FFF
H
T
A
= +25
°
C
PROPER OPERATION
WHEN V
SUPPLY
VOLTAGE IS ABOVE
CURVE
Figure 7. Minimum Supply Voltage
vs. Load Current
100
90
10
0%
2
100μs/DIV
T
A
= +25
°
C
NBW = 1MHz
Figure 10. Broadband Noise
1
10
1000
100
100
1
0.1
10
0.01
+85
°
C
–55
°
C
+25
°
C
V
= +5V
DATA = 000
H
V
IH
= 5.0V
V
IL
= 0.0V
OUTPUT SINK CURRENT – μA
O
Figure 8. Pull-Down Voltage vs. Out-
put Sink Current Capability
9
8
7
6
5
4
3
2
1
0
0
1
3
4
5
2
V
DD
= +4.5V
V
DD
= +5V
T
A
= +25
°
C
S
D
LOGIC INPUT VOLTAGE V
IN
H – Volts
Figure 11. Supply Current vs. Logic
Input Voltage
Typical Performance Characteristics
is possible down to +4.3 V. T he minimum operating supply
voltage versus load current plot, in Figure 7, provides informa-
tion for operation below V
DD
= +4.5 V.
T IMING AND CONT ROL
T he AD8522 has a 16-bit serial input register that accepts
clocked in data when the CS pin is active low. T he DAC regis-
ters are updated by the Load Enable (
LDA
and
LDB
) pins.
T he AD8522 offers two modes of data loading. T he first mode,
hardware-load, directs the data currently clocked into the serial
shift register into either the DAC A or the DAC B register or
both depending on the external active low strobing of the
LDA
or
LDB
pin. Serial data register bit Sf/
Hd
must be low for this
mode to be in effect.
T he second mode of operation is software-load which is de-
signed to minimize the number of control lines connected to
the AD8522. In this mode of operation the
LDA
and
LDB
pins
act as one control input taking the present contents of the serial
–6–
REV. A
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